MC9S12C128MFAE Freescale Semiconductor, MC9S12C128MFAE Datasheet - Page 210
![IC MCU 128K FLASH 25MHZ 48-LQFP](/photos/12/20/122066/mc9s12c128mfae_sml.jpg)
MC9S12C128MFAE
Manufacturer Part Number
MC9S12C128MFAE
Description
IC MCU 128K FLASH 25MHZ 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Specifications of MC9S12C128MFAE
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
31
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
Processor Series
S12C
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
4 KB
Interface Type
CAN/SCI/SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
31
Number Of Timers
8
Operating Supply Voltage
3.3 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
M68EVB912C32EE
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Package
48LQFP
Family Name
HCS12
Maximum Speed
25 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12C128MFAE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Chapter 7 Debug Module (DBGV1) Block Description
7.3.2.10
210
Module Base + 0x002B
Starting address location affected by INITRG register setting.
Module Base + 0x002C
Starting address location affected by INITRG register setting.
Reset
Reset
Field
15:0
15:0
W
W
R
R
Bit 15
Bit 7
Comparator A Compare Bits — The comparator A compare bits control whether comparator A compares the
address bus bits [15:0] to a logic 1 or logic 0. See
0 Compare corresponding address bit to a logic 0
1 Compare corresponding address bit to a logic 1
Debug Comparator A Register (DBGCA)
15
NOTES:
1. In BKP mode, PAGSEL has no functionality. Therefore, set PAGSEL to 00 (reset state).
2. Current HCS12 implementations are limited to six PPAGE bits, PIX[5:0].
0
0
7
PORTK/XAB
Figure 7-16. Comparators A and B Extended Comparison in BKP Mode
DBGCXX
PPAGE
Figure 7-17. Debug Comparator A Register High (DBGCAH)
Figure 7-18. Debug Comparator A Register Low (DBGCAL)
Bit 14
Bit 6
14
0
0
6
XAB21
PIX7
SEE NOTE 1
SEE NOTE 2
0
PAGSEL
Table 7-21. DBGCA Field Descriptions
XAB20
PIX6
Bit 13
MC9S12C-Family / MC9S12GC-Family
0
Bit 5
13
0
0
5
XAB19
PIX5
5
Rev 01.24
Bit 12
Bit 4
12
0
0
XAB18
4
PIX4
4
Description
Table
XAB17
PIX3
7-20.
3
Bit 11
Bit 3
EXTCMP
11
0
0
3
XAB16
PIX2
2
Bit 10
Bit 2
XAB15
10
0
0
2
PIX1
1
XAB14
BIT 0
PIX0
Freescale Semiconductor
Bit 9
Bit 1
0
0
9
1
Bit 8
Bit 0
0
0
8
0
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