MC9S12C128MFAE Freescale Semiconductor, MC9S12C128MFAE Datasheet - Page 264
![IC MCU 128K FLASH 25MHZ 48-LQFP](/photos/12/20/122066/mc9s12c128mfae_sml.jpg)
MC9S12C128MFAE
Manufacturer Part Number
MC9S12C128MFAE
Description
IC MCU 128K FLASH 25MHZ 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Specifications of MC9S12C128MFAE
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
31
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
Processor Series
S12C
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
4 KB
Interface Type
CAN/SCI/SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
31
Number Of Timers
8
Operating Supply Voltage
3.3 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
M68EVB912C32EE
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Package
48LQFP
Family Name
HCS12
Maximum Speed
25 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12C128MFAE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
9.3.2.9
This register controls the COP (computer operating properly) watchdog.
Read: anytime
Write: WCOP, CR2, CR1, CR0: once in user mode, anytime in special mode
Write: RSBCK: once
264
Module Base + 0x0008
RSBCK
CR[2:0]
Reset
WCOP
Field
2:0
7
6
W
R
WCOP
Window COP Mode Bit — When set, a write to the ARMCOP register must occur in the last 25% of the selected
period. A write during the first 75% of the selected period will reset the part. As long as all writes occur during
this window, 0x0055 can be written as often as desired. As soon as 0x00AA is written after the 0x0055, the time-
out logic restarts and the user must wait until the next window before writing to ARMCOP.
exact duration of this window for the seven available COP rates.
0 Normal COP operation
1 Window COP operation
COP and RTI Stop in Active BDM Mode Bit
0 Allows the COP and RTI to keep running in active BDM mode.
1 Stops the COP and RTI counters whenever the part is in active BDM mode.
COP Watchdog Timer Rate Select — These bits select the COP time-out rate (see
out period is OSCCLK period divided by CR[2:0] value. Writing a nonzero value to CR[2:0] enables the COP
counter and starts the time-out period. A COP counter time-out causes a system reset. This can be avoided by
periodically (before time-out) reinitializing the COP counter via the ARMCOP register.
CRG COP Control Register (COPCTL)
0
7
= Unimplemented or Reserved
1. OSCCLK cycles are referenced from the previous COP time-out reset
RSBCK
(writing 0x0055/0x00AA to the ARMCOP register)
CR2
0
6
0
0
0
0
1
1
1
1
Figure 9-12. CRG COP Control Register (COPCTL)
Table 9-8. COPCTL Field Descriptions
CR1
0
0
1
1
0
0
1
1
Table 9-9. COP Watchdog Rates
MC9S12C-Family / MC9S12GC-Family
0
0
5
CR0
0
1
0
1
0
1
0
1
Rev 01.24
0
0
4
Description
Cycles to Time Out
COP disabled
OSCCLK
0
0
3
2
2
2
2
2
2
2
14
16
18
20
22
23
24
(1)
CR2
0
2
Table
Freescale Semiconductor
CR1
0
1
Table 9-9
9-9). The COP time-
shows the
CR0
0
0
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