MC9S12C128MFAE Freescale Semiconductor, MC9S12C128MFAE Datasheet - Page 109
![IC MCU 128K FLASH 25MHZ 48-LQFP](/photos/12/20/122066/mc9s12c128mfae_sml.jpg)
MC9S12C128MFAE
Manufacturer Part Number
MC9S12C128MFAE
Description
IC MCU 128K FLASH 25MHZ 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Specifications of MC9S12C128MFAE
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
31
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
Processor Series
S12C
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
4 KB
Interface Type
CAN/SCI/SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
31
Number Of Timers
8
Operating Supply Voltage
3.3 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
M68EVB912C32EE
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Package
48LQFP
Family Name
HCS12
Maximum Speed
25 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12C128MFAE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Chapter 3
Module Mapping Control (MMCV4) Block Description
3.1
This section describes the functionality of the module mapping control (MMC) sub-block of the S12 core
platform.
The block diagram of the MMC is shown in
The MMC is the sub-module which controls memory map assignment and selection of internal resources
and external space. Internal buses between the core and memories and between the core and peripherals is
controlled in this module. The memory expansion is generated in this module.
Freescale Semiconductor
EBI ALTERNATE WRITE DATA BUS
EBI ALTERNATE READ DATA BUS
EBI ALTERNATE ADDRESS BUS
READ & WRITE ENABLES
CPU WRITE DATA BUS
CPU READ DATA BUS
MODE INFORMATION
CPU ADDRESS BUS
BDM_UNSECURE
CLOCKS, RESET
CPU CONTROL
Introduction
STOP, WAIT
SECURE
REGISTERS
MC9S12C-Family / MC9S12GC-Family
Figure 3-1. MMC Block Diagram
Figure
BUS CONTROL
SECURITY
Rev 01.24
MMC
3-1.
INTERNAL MEMORY
ADDRESS DECODE
EXPANSION
ALTERNATE WRITE DATA BUS (BDM)
ALTERNATE READ DATA BUS (BDM)
ALTERNATE ADDRESS BUS (BDM)
MEMORY SPACE SELECT(S)
PERIPHERAL SELECT
PORT K INTERFACE
CORE SELECT (S)
MMC_SECURE
109
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