MC9S12C128MFAE Freescale Semiconductor, MC9S12C128MFAE Datasheet - Page 160
![IC MCU 128K FLASH 25MHZ 48-LQFP](/photos/12/20/122066/mc9s12c128mfae_sml.jpg)
MC9S12C128MFAE
Manufacturer Part Number
MC9S12C128MFAE
Description
IC MCU 128K FLASH 25MHZ 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Specifications of MC9S12C128MFAE
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
31
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
Processor Series
S12C
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
4 KB
Interface Type
CAN/SCI/SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
31
Number Of Timers
8
Operating Supply Voltage
3.3 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
M68EVB912C32EE
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Package
48LQFP
Family Name
HCS12
Maximum Speed
25 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12C128MFAE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Chapter 5 Interrupt (INTV1) Block Description
5.3.2.2
Read: Only in special modes. Reads will return either the state of the interrupt inputs of the interrupt sub-
block (WRTINT = 0) or the values written into the TEST registers (WRTINT = 1). Reads will always
return 0s in normal modes.
Write: Only in special modes and with WRTINT = 1 and CCR I mask = 1.
160
Module Base + 0x0016
Starting address location affected by INITRG register setting.
ADR[3:0]
WRTINT
Reset
Field
3:0
4
W
R
INTE
Write to the Interrupt Test Registers
Read: anytime
Write: only in special modes and with I-bit mask and X-bit mask set.
0 Disables writes to the test registers; reads of the test registers will return the state of the interrupt inputs.
1 Disconnect the interrupt inputs from the priority decoder and use the values written into the ITEST registers
Note: Any interrupts which are pending at the time that WRTINT is set will remain until they are overwritten.
Test Register Select Bits
Read: anytime
Write: anytime
These bits determine which test register is selected on a read or write. The hexadecimal value written here will
be the same as the upper nibble of the lower byte of the vector selects. That is, an “F” written into ADR[3:0] will
select vectors 0xFFFE–0xFFF0 while a “7” written to ADR[3:0] will select vectors 0xFF7E–0xFF70.
Interrupt Test Registers
0
7
instead.
= Unimplemented or Reserved
INTC
0
6
Figure 5-3. Interrupt TEST Registers (ITEST)
Table 5-2. ITCR Field Descriptions
MC9S12C-Family / MC9S12GC-Family
INTA
0
5
Rev 01.24
INT8
0
4
Description
INT6
0
3
INT4
0
2
Freescale Semiconductor
INT2
0
1
INT0
0
0
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