MC9S12C128MFAE Freescale Semiconductor, MC9S12C128MFAE Datasheet - Page 521
![IC MCU 128K FLASH 25MHZ 48-LQFP](/photos/12/20/122066/mc9s12c128mfae_sml.jpg)
MC9S12C128MFAE
Manufacturer Part Number
MC9S12C128MFAE
Description
IC MCU 128K FLASH 25MHZ 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Specifications of MC9S12C128MFAE
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
31
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
Processor Series
S12C
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
4 KB
Interface Type
CAN/SCI/SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
31
Number Of Timers
8
Operating Supply Voltage
3.3 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
M68EVB912C32EE
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Package
48LQFP
Family Name
HCS12
Maximum Speed
25 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12C128MFAE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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then FCLKDIV register bits PRDIV8 and FDIV[5:0] are to be set as described in
For example, if the oscillator clock frequency is 950 kHz and the bus clock is 10 MHz, FCLKDIV bits
FDIV[5:0] should be set to 4 (000100) and bit PRDIV8 set to 0. The resulting FCLK is then 190 kHz. As
a result, the Flash algorithm timings are increased over optimum target by:
Command execution time will increase proportionally with the period of FCLK.
If the FCLKDIV register is written, the bit FDIVLD is set automatically. If the FDIVLD bit is 0, the
FCLKDIV register has not been written since the last reset. If the FCLKDIV register has not been written
to, the Flash command loaded during a command write sequence will not execute and the ACCERR flag
in the FSTAT register will set.
Freescale Semiconductor
(
200 190
–
Because of the impact of clock synchronization on the accuracy of the
functional timings, programming or erasing the Flash array cannot be
performed if the bus clock runs at less than 1 MHz. Programming or erasing
the Flash array with an input clock < 150 kHz should be avoided. Setting
FCLKDIV to a value such that FCLK < 150 kHz can destroy the Flash array
due to overstress. Setting FCLKDIV to a value such that (1/FCLK + Tbus)
< 5µs can result in incomplete programming or erasure of the Flash array
cells.
) 200
⁄
×
100
=
5%
MC9S12C-Family / MC9S12GC-Family
CAUTION
Rev 01.24
Chapter 18 32 Kbyte Flash Module (S12FTS32KV1)
Figure
18-21.
521
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