MC9S12C128MFAE Freescale Semiconductor, MC9S12C128MFAE Datasheet - Page 643
![IC MCU 128K FLASH 25MHZ 48-LQFP](/photos/12/20/122066/mc9s12c128mfae_sml.jpg)
MC9S12C128MFAE
Manufacturer Part Number
MC9S12C128MFAE
Description
IC MCU 128K FLASH 25MHZ 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Specifications of MC9S12C128MFAE
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
31
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
Processor Series
S12C
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
4 KB
Interface Type
CAN/SCI/SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
31
Number Of Timers
8
Operating Supply Voltage
3.3 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
M68EVB912C32EE
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Package
48LQFP
Family Name
HCS12
Maximum Speed
25 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12C128MFAE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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21.4.1.4
21.4.1.4.1
The ACCERR flag in the FSTAT register will be set during the command write sequence if any of the
following illegal Flash operations are performed causing the command write sequence to immediately
abort:
The ACCERR flag will not be set if any Flash register is read during the command write sequence. If the
Flash array is read during execution of an algorithm (CCIF=0), the Flash module will return invalid data
and the ACCERR flag will not be set. If an ACCERR flag is set in the FSTAT register, the Flash command
controller is locked. It is not possible to launch another command until the ACCERR flag is cleared.
21.4.1.4.2
The PVIOL flag in the FSTAT register will be set during the command write sequence after the word write
to the Flash address space if any of the following illegal Flash operations are performed, causing the
command write sequence to immediately abort:
If the PVIOL flag is set, the Flash command controller is locked. It is not possible to launch another
command until the PVIOL flag is cleared.
Freescale Semiconductor
1. Writing to the Flash address space before initializing the FCLKDIV register
2. Writing a misaligned word or a byte to the valid Flash address space
3. Writing to the Flash address space while CBEIF is not set
4. Writing a second word to the Flash address space before executing a program or erase command
5. Writing to any Flash register other than FCMD after writing a word to the Flash address space
6. Writing a second command to the FCMD register before executing the previously written
7. Writing an invalid command to the FCMD register
8. Writing to any Flash register other than FSTAT (to clear CBEIF) after writing to the FCMD register
9. The part enters stop mode and a program or erase command is in progress. The command is aborted
10. When security is enabled, a command other than mass erase originating from a non-secure memory
11. A 0 is written to the CBEIF bit in the FSTAT register to abort a command write sequence.
1. Writing a Flash address to program in a protected area of the Flash array (see
2. Writing a Flash address to erase in a protected area of the Flash array.
3. Writing the mass erase command to the FCMD register while any protection is enabled.
on the previously written word
command
and any pending command is killed
or from the background debug mode is written to the FCMD register
Illegal Flash Operations
Access Error
Protection Violation
MC9S12C-Family / MC9S12GC-Family
Rev 01.24
Chapter 21 128 Kbyte Flash Module (S12FTS128K1V1)
Section
21.3.2.5).
643
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