MC9S12C128MFAE Freescale Semiconductor, MC9S12C128MFAE Datasheet - Page 380
![IC MCU 128K FLASH 25MHZ 48-LQFP](/photos/12/20/122066/mc9s12c128mfae_sml.jpg)
MC9S12C128MFAE
Manufacturer Part Number
MC9S12C128MFAE
Description
IC MCU 128K FLASH 25MHZ 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Specifications of MC9S12C128MFAE
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
31
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
Processor Series
S12C
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
4 KB
Interface Type
CAN/SCI/SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
31
Number Of Timers
8
Operating Supply Voltage
3.3 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
M68EVB912C32EE
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Package
48LQFP
Family Name
HCS12
Maximum Speed
25 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12C128MFAE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description
When using the 16-bit concatenated mode, the clock source is determined by the low-order 8-bit channel
clock select control bits. That is channel 5 when channels 4 and 5 are concatenated, channel 3 when
channels 2 and 3 are concatenated, and channel 1 when channels 0 and 1 are concatenated. The resulting
PWM is output to the pins of the corresponding low-order 8-bit channel as also shown in
The polarity of the resulting PWM output is controlled by the PPOLx bit of the corresponding low-order
8-bit channel as well.
After concatenated mode is enabled (CONxx bits set in PWMCTL register), enabling/disabling the
corresponding 16-bit PWM channel is controlled by the low-order PWMEx bit. In this case, the high-order
bytes PWMEx bits have no effect and their corresponding PWM output is disabled.
In concatenated mode, writes to the 16-bit counter by using a 16-bit access or writes to either the low or
high-order byte of the counter will reset the 16-bit counter. Reads of the 16-bit counter must be made by
16-bit access to maintain data coherency.
Either left aligned or center aligned output mode can be used in concatenated mode and is controlled by
the low-order CAEx bit. The high-order CAEx bit has no effect.
380
Clock Source 5
Clock Source 3
Clock Source 1
MC9S12C-Family / MC9S12GC-Family
Figure 12-40. PWM 16-Bit Mode
PWMCNT4
PWMCNT2
PWMCNT0
High
High
High
Period/Duty Compare
Period/Duty Compare
Period/Duty Compare
Rev 01.24
PWCNT5
PWCNT3
PWCNT1
Low
Low
Low
PWM5
PWM3
PWM1
Freescale Semiconductor
Figure
12-40.
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