MC9S12C128MFAE Freescale Semiconductor, MC9S12C128MFAE Datasheet - Page 113
![IC MCU 128K FLASH 25MHZ 48-LQFP](/photos/12/20/122066/mc9s12c128mfae_sml.jpg)
MC9S12C128MFAE
Manufacturer Part Number
MC9S12C128MFAE
Description
IC MCU 128K FLASH 25MHZ 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Specifications of MC9S12C128MFAE
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
31
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
Processor Series
S12C
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
4 KB
Interface Type
CAN/SCI/SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
31
Number Of Timers
8
Operating Supply Voltage
3.3 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
M68EVB912C32EE
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Package
48LQFP
Family Name
HCS12
Maximum Speed
25 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12C128MFAE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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3.3.2.1
Read: Anytime
Write: Once in normal and emulation modes, anytime in special modes
This register initializes the position of the internal RAM within the on-chip system memory map.
Freescale Semiconductor
Module Base + 0x0010
Starting address location affected by INITRG register setting.
RAM[15:11]
RAMHAL
Reset
Field
7:3
0
W
R
RAM15
Internal RAM Map Position — These bits determine the upper five bits of the base address for the system’s
internal RAM array.
RAM High-Align — RAMHAL specifies the alignment of the internal RAM array.
0 Aligns the RAM to the lowest address (0x0000) of the mappable space
1 Aligns the RAM to the higher address (0xFFFF) of the mappable space
Initialization of Internal RAM Position Register (INITRM)
0
7
Writes to this register take one cycle to go into effect.
Figure 3-3. Initialization of Internal RAM Position Register (INITRM)
= Unimplemented or Reserved
RAM14
0
6
Table 3-2. INITRM Field Descriptions
RAM13
MC9S12C-Family / MC9S12GC-Family
0
5
RAM12
Rev 01.24
NOTE
0
4
Description
Chapter 3 Module Mapping Control (MMCV4) Block Description
RAM11
1
3
0
0
2
0
0
1
RAMHAL
1
0
113
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