MC9S12C128MFAE Freescale Semiconductor, MC9S12C128MFAE Datasheet - Page 170
![IC MCU 128K FLASH 25MHZ 48-LQFP](/photos/12/20/122066/mc9s12c128mfae_sml.jpg)
MC9S12C128MFAE
Manufacturer Part Number
MC9S12C128MFAE
Description
IC MCU 128K FLASH 25MHZ 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Specifications of MC9S12C128MFAE
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
31
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
Processor Series
S12C
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
4 KB
Interface Type
CAN/SCI/SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
31
Number Of Timers
8
Operating Supply Voltage
3.3 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
M68EVB912C32EE
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Package
48LQFP
Family Name
HCS12
Maximum Speed
25 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12C128MFAE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Chapter 6 Background Debug Module (BDMV4) Block Description
6.3.2.1
Note:
1. ENBDM is read as "1" by a debugging environment in Special single-chip mode when the device is not secured or secured
2. UNSEC is read as "1" by a debugging environment in Special single-chip mode when the device is secured and fully erased,
Read: All modes through BDM operation
Write: All modes but subject to the following:
170
0xFF01
Special single-chip mode:
Special peripheral mode:
but fully erased (Flash and EEPROM).This is because the ENBDM bit is set by the standard firmware before a BDM command
can be fully transmitted and executed.
else it is "0" and can only be read if not secure (see also bit description).
•
•
•
•
BDMACT can only be set by BDM hardware upon entry into BDM. It can only be cleared by the
standard BDM firmware lookup table upon exit from BDM active mode.
CLKSW can only be written via BDM hardware or standard BDM firmware write commands.
All other bits, while writable via BDM hardware or standard BDM firmware write commands,
should only be altered by the BDM hardware or standard firmware lookup table as part of BDM
command execution.
ENBDM should only be set via a BDM hardware command if the BDM firmware commands are
needed. (This does not apply in special single-chip mode).
All other modes:
BDM Status Register (BDMSTS)
Reset:
W
R
ENBDM
1
7
0
0
0
(1)
Figure 6-3. BDM Status Register (BDMSTS)
= Unimplemented or Reserved
BDMACT
MC9S12C-Family / MC9S12GC-Family
1
1
1
0
6
ENTAG
5
0
0
0
0
Rev 01.24
SDV
0
0
0
0
4
TRACE
3
0
0
0
0
= Implemented (do not alter)
CLKSW
0
0
0
0
2
Freescale Semiconductor
UNSEC
0
1
0
0
0
(2)
0
0
0
0
0
0
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