MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 238

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

6.13.4 System Timer Registers
6.13.4.1 Decrementer Register
DEC — Decrementer Register
6.13.4.2 Time Base SPRs
MPC555
USER’S MANUAL
HRESET/SRESET: UNCHANGED
0
Bit(s)
20:25
28:31
MSB
0:17
18
19
26
27
0
The following sections describe registers associated with the system timers. These fa-
cilities are powered by the KAPWR and can preserve their value when the main power
supply is off. Refer to
order to guarantee this data retention.
The 32-bit decrementer register is defined by the MPC555 / MPC556 architecture. The
values stored in this register are used by a down counter to cause decrementer excep-
tions. The decrementer causes an exception whenever bit zero changes from a logic
zero to a logic one. A read of this register always returns the current count value from
the down counter.
Contents of this register can be read or written to by the mfspr or the mtspr instruc-
tion. The decrementer register is reset by PORESET. HRESET and SRESET do not
affect this register. The decrementer is powered by standby power and can continue
to count when standby power is applied.
Refer to
The TB is a 64-bit register containing a 64-bit integer that is incremented periodically.
There is no automatic initialization of the TB; the system software must perform this
0
0
/
0
MPC556
Name
DEXT
IBMT
IEXT
DBM
—
—
—
0
3.9.5 Decrementer Register (DEC)
0
Reserved
Instruction external transfer error acknowledge. This bit is set if the cycle was terminated by an
externally generated TEA signal when an instruction fetch was initiated.
Instruction transfer monitor time out. This bit is set if the cycle was terminated by a bus monitor
time-out when an instruction fetch was initiated.
Reserved
Data external transfer error acknowledge. This bit is set if the cycle was terminated by an exter-
nally generated TEA signal when a data load or store is requested by an internal master.
Data transfer monitor time out. This bit is set if the cycle was terminated by a bus monitor time-
out when a data load or store is requested by an internal master.
Reserved
0
0
0
Freescale Semiconductor, Inc.
SYSTEM CONFIGURATION AND PROTECTION
For More Information On This Product,
8.3.3 Pre-Divider
0
Table 6-15 TESR Bit Descriptions
0
0
Go to: www.freescale.com
0
Rev. 15 October 2000
Decrementing Counter
0
0
PORESET
0
for details on the required actions needed in
0
0
Description
for more information on this register.
0
0
0
0
0
0
0
0
0
0
MOTOROLA
0
SPR 22
0
0
LSB
6-30
31
0