MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 45

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

Freescale Semiconductor, Inc.
Page
Table
Number
Number
19-3 CMFTST Bit Descriptions .................................................................................. 19-8
19-4 CMF Programming Algorithm (v6 and Later)..................................................... 19-8
19-5 CMF Erase Algorithm (v6) ................................................................................. 19-9
19-6 CMFCTL Bit Descriptions ................................................................................ 19-10
19-7 EEPROM Array Addressing............................................................................. 19-12
19-8 CMF EEPROM Array Address Fields .............................................................. 19-12
19-9 Program Interlock State Descriptions .............................................................. 19-21
19-10 Results of Programming Margin Read........................................................... 19-22
19-11 Erase Interlock State Descriptions................................................................. 19-26
19-12 System Clock Range ..................................................................................... 19-28
19-13 Clock Period Exponent and Pulse Width Range ........................................... 19-29
19-14 Censorship Control Bits ................................................................................. 19-31
19-15 Levels of Censorship ..................................................................................... 19-32
19-16 CMF EEPROM Devices Modes and Censorship Status ............................... 19-33
19-17 NVM Fuse States........................................................................................... 19-34
20-1 SRAMMCR Bit Descriptions ............................................................................. 20-3
21-1 VF Pins Instruction Encodings.......................................................................... 21-3
21-2 VF Pins Queue Flush Encodings....................................................................... 21-4
21-3 VFLS Pin Encodings.......................................................................................... 21-4
21-4 Detecting the Trace Buffer Start Point ............................................................... 21-7
21-5 Fetch Show Cycles Control ............................................................................... 21-8
21-6 Instruction Watchpoints Programming Options ............................................... 21-17
21-7 Load/Store Data Events................................................................................... 21-18
21-8 Load/Store Watchpoints Programming Options .............................................. 21-19
21-9 The Check Stop State and Debug Mode ......................................................... 21-29
21-10 Trap Enable Data Shifted into Development Port Shift Register ................... 21-38
21-11 Debug Port Command Shifted Into Development Port Shift Register ........... 21-38
21-12 Status / Data Shifted Out of Development Port Shift Register....................... 21-39
21-13 Debug Instructions / Data Shifted Into Development Port Shift Register....... 21-40
21-14 Development Support Programming Model................................................... 21-44
21-15 Development Support Registers Read Access Protection ............................ 21-45
21-16 Development Support Registers Write Access Protection............................. 21-45
21-17 CMPA-CMPD Bit Descriptions....................................................................... 21-45
21-18 CMPE-CMPF Bit Descriptions ....................................................................... 21-46
21-19 BAR Bit Descriptions ..................................................................................... 21-46
21-20 CMPG-CMPH Bit Descriptions ...................................................................... 21-46
21-21 ICTRL Bit Descriptions .................................................................................. 21-48
21-22 ISCT_SER Bit Descriptions ........................................................................... 21-49
21-23 LCTRL1 Bit Descriptions ............................................................................... 21-50
21-24 LCTRL2 Bit Descriptions ............................................................................... 21-51
21-25 Breakpoint Counter A Value and Control Register (COUNTA)...................... 21-52
21-26 Breakpoint Counter B Value and Control Register (COUNTB)..................... 21-53
21-27 ECR Bit Descriptions ..................................................................................... 21-54
21-28 DER Bit Descriptions ..................................................................................... 21-55
MPC555 / MPC556
LIST OF TABLES
MOTOROLA
USER’S MANUAL
Rev. 15 October 2000
xlv
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