MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 381

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

MPC555
USER’S MANUAL
Bit(s)
17:19
20:21
24:25
0:16
22
23
26
27
28
29
30
31
/
WEBS
TBDIP
LBDIP
MPC556
Name
SETA
WP
BA
AT
PS
—
—
BI
V
Base address. These bits are compared to the corresponding unmasked address signals among
ADDR[0:16] to determine if a memory bank controlled by the memory controller is being access-
ed by an internal bus master. (The address types are also compared.) These bits are used in
conjunction with the AM[0:16] bits in the OR.
Address type. This field can be used to require accesses of the memory bank to be limited to a
certain address space type. These bits are used in conjunction with the ATM bits in the OR. Note
that the address type field uses only AT[0:2] and does not need AT[3] to define the memory type
space. For a full definition of address types, refer to
Port size
00 = 32-bit port
01 = 8-bit port
10 = 16-bit port
11 = Reserved
Reserved
Write protect. An attempt to write to the range of addresses specified in a base address register
that has this bit set can cause the TEA signal to be asserted by the bus-monitor logic (if enabled),
causing termination of this cycle.
0 = Both read and write accesses are allowed
1 = Only read accesses are allowed. The CSx signal and TA are not asserted by the memory
Reserved
Write-enable/byte-select. This bit controls the functionality of the WE/BE pads.
0 = The WE/BE pads operate as WE
1 = The WE/BE pads operate as BE
Toggle-burst data in progress. TBDIP determines how long the BDIP strobe will be asserted for
each data beat in the burst cycles.
Late-burst-data-in-progress (LBDIP). This bit determines the timing of the first assertion of the
BDIP pin in burst cycles.
Note: it is not allowed to set both LBDIP and TBDIP bits in a region’s base registers; the behavior
of the design in such cases is unpredictable.
0 = Normal timing for BDIP assertion (asserts one clock after negation of TS
1 = Late timing for BDIP assertion (asserts after the programmed number of wait states
External transfer acknowledge
0 = TA generated internally by memory controller
1 = TA generated by external logic. Note that programming the timing of CS/WE/OE strobes may
Burst inhibit
0 = Memory controller drives BI negated (high). The bank supports burst accesses.
1 = Memory controller drives BI asserted (low). The bank does not support burst accesses.
Note: Following a system reset, the BI bit is set in OR0.
Valid bit. When set, this bit indicates that the contents of the base-register and option-register
pair are valid. The CS signal does not assert until the V-bit is set. Note that an access to a region
that has no V-bit set may cause a bus monitor timeout. Note also that following a system reset,
the V-bit in BR0 reflects the value of ID3 in the reset configuration word.
controller on write cycles to this memory bank. WPER is set in the MSTAT register if a write
to this memory bank is attempted
have no meaning when this bit is set
Freescale Semiconductor, Inc.
Table 10-7 BR0 – BR3 Bit Descriptions
For More Information On This Product,
Go to: www.freescale.com
MEMORY CONTROLLER
Rev. 15 October 2000
Description
9.5.7.6 Address
Types.
MOTOROLA
10-29