MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 239

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

TB — Time Base (Reading)
TB — Time Base (Writing)
6.13.4.3 Time Base Reference Registers
TBREF0 — Time Base Reference Register 0
TBREF1 — Time Base Reference Register 1
6.13.4.4 Time Base Control and Status Register
MPC555
USER’S MANUAL
MSB
MSB
MSB
MSB
0
0
0
0
initialization. The contents of the register may be written by the mttbl or the mttbu in-
structions, see
Refer to
(TB) — OEA
Two reference registers (TBREF0 and TBREF1) are associated with the lower part of
the time base (TBL). Each is a 32-bit read/write register. Upon a match between the
contents of TBL and the reference register, a maskable interrupt is generated.
The TBSCR is 16-bit read/write register. It controls the TB, decrementer count enable,
and interrupt generation and is used for reporting the source of the interrupts. The reg-
ister can be read anytime. A status bit is cleared by writing a one to it. (Writing a zero
has no effect.) More than one bit can be cleared at a time.
/
MPC556
3.8 PowerPC VEA Register Set — Time Base
for more information on reading and writing the TBU and TBL registers.
3.9.4 Time Base Facility (TB) —
TBU
TBU
Freescale Semiconductor, Inc.
SYSTEM CONFIGURATION AND PROTECTION
For More Information On This Product,
Go to: www.freescale.com
Rev. 15 October 2000
RESET: UNCHANGED
RESET: UNCHANGED
TBREF0
TBREF1
RESET:
RESET:
31 32
31 32
OEA.
and
3.9.4 Time Base Facility
TBL
TBL
SPR 268, 269
SPR 284, 285
0x2F C204
0x2F C208
MOTOROLA
LSB
LSB
LSB
6-31
63
63
31
LSB
31