MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 408

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

12.4.4 Interrupt Synchronizer
MPC555
USER’S MANUAL
ILBS [0:1]
The interrupt synchronizer latches the 32 levels of interrupts from the IMB bus into a
register which can be read by the CPU or other U-bus master. Since there are only
eight lines for interrupts on the IMB and 32 levels of interrupts are possible, the 32 in-
terrupt levels are multiplexed onto eight IMB interrupt lines. Apart from latching these
interrupts in the register (UIPEND register), the interrupt synchronizer drives the inter-
rupts onto the U-bus, where they are latched by the interrupt controller in the USIU.
If IMB modules drive interrupts on any of the 24 levels (levels eight through 31), they
will be latched in the Interrupt pending register (UIPEND) in the UIMB. If any of the reg-
ister bits 7 to 31 are set, then bit 7 will be set as well. Software must poll this register
to find out which of the levels 7 to 31 are asserted.
The UIPEND register contains a status bit for each of the 32 interrupt levels. Each bit
of the register is a read-only status bit, reflecting the current state of the corresponding
interrupt signal. For each of the 32 interrupt levels, a corresponding bit of the UIPEND
register is set.
Figure 12-4
to represent 32 levels of interrupts.
terrupt synchronizer.
/
IMBCLOCK
MPC556
RESET
shows how the eight interrupt lines are connected to the UIPEND register
Figure 12-6 Interrupt Synchronizer Block diagram
Machine
State
Freescale Semiconductor, Inc.
IMB LVL [0:7]
For More Information On This Product,
U-BUS TO IMB3 BUS INTERFACE (UIMB)
4
Go to: www.freescale.com
Rev. 15 October 2000
Figure 12-6
UIPEND
LVL 8-31
LVL 0-7
shows the implementation of the in-
LVL7
24
32
U-bus Interrupt Level[0:7]
7
U-bus
Data[0:31]
OR
8
MOTOROLA
12-6