MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 622

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

17.3.3 Interchannel Communication
17.3.4 Programmable Channel Service Priority
17.3.5 Coherency
17.3.6 Emulation Support
MPC555
USER’S MANUAL
ation, so that any channel can be configured to perform any time function. Any function
can operate on the calling channel, and, under program control, on another channel
determined by the program or by a parameter. The user controls the combination of
time functions.
The autonomy of the TPU3 is enhanced by the ability of a channel to affect the oper-
ation of one or more other channels without CPU intervention. Interchannel communi-
cation can be accomplished by issuing a link service request to another channel, by
controlling another channel directly, or by accessing the parameter RAM of another
channel.
The TPU3 provides a programmable service priority level to each channel. Three pri-
ority levels are available. When more than one channel of a given priority requests ser-
vice at the same time, arbitration is accomplished according to channel number. To
prevent a single high-priority channel from permanently blocking other functions, other
service requests of the same priority are performed in channel order after the lowest-
numbered, highest-priority channel is serviced.
For data to be coherent, all available portions of the data must be identical in age, or
must be logically related. As an example, consider a 32-bit counter value that is read
and written as two 16-bit words. The 32-bit value is read-coherent only if both 16-bit
portions are updated at the same time, and write-coherent only if both portions take
effect at the same time. Parameter RAM hardware supports coherent access of two
adjacent 16-bit parameters. The host CPU must use a long-word operation to guaran-
tee coherency.
Although factory-programmed time functions can perform a wide variety of control
tasks, they may not be ideal for all applications. The TPU3 provides emulation capa-
bility that allows the user to develop new time functions. Emulation mode is entered by
setting the EMU bit in TPUMCR. In emulation mode, an auxiliary bus connection is
made between the DPTRAM and the TPU3, and access to DPTRAM via the intermod-
ule bus is disabled. A 9-bit address bus, a 32-bit data bus, and control lines transfer
information between the modules. To ensure exact emulation, DPTFLASH module ac-
cess timing remains consistent with access timing of the TPU microcode ROM control
store.
To support changing TPU application requirements, Motorola has established a TPU
function library. The function library is a collection of TPU functions written for easy as-
sembly in combination with each other or with custom functions. Refer to Motorola Pro-
gramming Note
(TPUPN00/D), for information about developing custom functions and accessing the
/
MPC556
Using the TPU Function Library and TPU Emulation Mode,
Freescale Semiconductor, Inc.
For More Information On This Product,
TIME PROCESSOR UNIT 3
Go to: www.freescale.com
Rev. 15 October 2000
MOTOROLA
17-4