EP9315-CBZ Cirrus Logic Inc, EP9315-CBZ Datasheet - Page 141
EP9315-CBZ
Manufacturer Part Number
EP9315-CBZ
Description
IC ARM9 SOC ENH UNIV 352PBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9315-CBZ
Core Size
16/32-Bit
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, PCMCIA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
352-BGA
Controller Family/series
(ARM9)
No. Of I/o's
16
Cpu Speed
200MHz
No. Of Timers
5
Digital Ic Case Style
BGA
Supply Voltage Range
1.65V To 1.94V, 3V To 3.6V
Embedded Interface Type
SPI
Rohs Compliant
Yes
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9315A-Z
Case
BGA
Dc
06+
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1144 - KIT DEVELOPMENT EP9315 ARM9
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1139
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP9315-CBZ
Manufacturer:
CIRRUS
Quantity:
20 000
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PwrCnt
DS785UM1
FIR_EN
31
15
Address:
Definition:
Bit Descriptions:
RSVD
30
14
BAUD
UART
29
13
USH_EN
28
12
RSTFLG:
TEST_RESET:
CLDFLG:
WDTFLG:
CHIPID:
CHIPMAN:
0x8093_0004 - Read / Write
The PwrCnt system control register is the Clock/Debug control status register.
RSVD:
DMA
M2M
CH1
27
11
DMA
M2M
CH0
26
10
Copyright 2007 Cirrus Logic
DMA
M2P
CH8
25
9
Reset flag. This bit is set if the user reset button has been
pressed; forcing the RSTOn input low. It is cleared by
writing to the STFClr location. On power-on-reset, it is
reset to 0b.
Test reset flag. This bit is set if the test reset has been
activated; it is cleared by writing to the STFClr location. On
power-on-reset, it is reset to 0b.
Cold start flag. This bit is set if the device has been reset
with a power-on-reset; it is cleared by writing to the STFClr
location. On power-on-reset, it is set to 1b.
Watchdog Timer flag. This bit is set if the Watchdog timer
resets the system. It is cleared by writing to the STFClr
location. It is reset to 0.
Chip ID bits. This 8-bit register determines the Chip
Identification for the device. For the device, this value is
0x20.
This 8-bit register determines the Chip Manufacturer ID for
the device. For the device, this value is 0x43.
Reserved. Unknown During Read.
DMA
M2P
CH9
24
8
RSVD
DMA
M2P
CH6
23
7
DMA
M2P
CH7
22
6
DMA
M2P
CH4
21
5
DMA
M2P
CH5
20
4
DMA
M2P
CH2
19
3
EP93xx User’s Guide
DMA
M2P
CH3
18
2
System Controller
DMA
M2P
CH0
17
1
DMA
M2P
CH1
16
0
5-15
5
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