EP9315-CBZ Cirrus Logic Inc, EP9315-CBZ Datasheet - Page 255

• Manufacturer Part Number: EP9315-CBZ
• Description: IC ARM9 SOC ENH UNIV 352PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9315-CBZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, PCMCIA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 352-BGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 16
• Cpu Speed: 200MHz
• No. Of Timers: 5
• Digital Ic Case Style: BGA
• Supply Voltage Range: 1.65V To 1.94V, 3V To 3.6V
• Embedded Interface Type: SPI
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9315A-Z
• Case: BGA
• Dc: 06+
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1144 - KIT DEVELOPMENT EP9315 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1139

LUT Registers
GrySclLUTR,
GrySclLUTG,
DS785UM1
GrySclLUTB
31
15
Address:
Default:
Definition: Grayscale Look-Up-Tables
Bit Descriptions:
30
14
29
13
28
12
RATE:
GrySclLUTR - 0x8003_0080 through 0x8003_00FC
GrySclLUTG - 0x8003_0280 through 0x8003_02FC
GrySclLUTB - 0x8003_0300 through 0x8003_037C
0x0000_FFFF in offset locations 0x7, 0x15, 0x23, and 0x31
0x0000_0000 in all other locations
RSVD:
FRAME:
27
11
26
10
Copyright 2007 Cirrus Logic
RSVD
25
9
When EN = ‘0’ and the 2-bit cursor pixel fetched from
SDRAM is ‘10’,
cursor image.
When EN = ‘0’ and the 2-bit cursor pixel fetched from
SDRAM is ‘11’,
cursor image.
Rate - Read/Write
When EN = ‘1’, the Rate value written to this field specifies
the number of video frames that will occur before switching
between CursorColor1 or CursorColor2, and
CursorBlinkColor1 or CursorBlinkColor2, respectively.
An on/off cursor blink cycle is controlled by the equation:
Blink Cycle =
Reserved - Unknown during read
Frame Counter Selection - Read/Write
Raster Engine With Analog/LCD Integrated Timing and Interface
24
8
D
23
7
2 x (1/VCLK) x HClkTotal.Total x
CursorColor1,
CursorColor1,
22
6
21
5
VLinesTotal.Total x (255 - RATE)
20
is used for the non-blinking
4
is used for the non-blinking
19
3
EP93xx User’s Guide
FRAME
18
2
VERT
17
1
HORZ
16
7-73
0
7