EP9315-CBZ Cirrus Logic Inc, EP9315-CBZ Datasheet - Page 681

• Manufacturer Part Number: EP9315-CBZ
• Description: IC ARM9 SOC ENH UNIV 352PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9315-CBZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, PCMCIA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 352-BGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 16
• Cpu Speed: 200MHz
• No. Of Timers: 5
• Digital Ic Case Style: BGA
• Supply Voltage Range: 1.65V To 1.94V, 3V To 3.6V
• Embedded Interface Type: SPI
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9315A-Z
• Case: BGA
• Dc: 06+
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1144 - KIT DEVELOPMENT EP9315 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1139

I2SRX2En
DS785UM1
21.7.3 I
31
15
Bit Descriptions:
Address:
Default:
D
Bit Descriptions:
efinition:
30
14
2
S Configuration and Status Registers
29
13
0x8082_000C
0x8082_0000
0x8082_0004
0x8082_0008
Address
28
12
RSVD:
i2s_rx1_EN:
0x8082_006C - Read/Write
0x0000_0000
RX2 Channel Enable
RSVD:
i2s_rx2_EN:
27
11
Type
R/W
R/W
R/W
R/W
Table 21-9. I
26
10
Width
20
Copyright 2007 Cirrus Logic
7
7
2
25
9
Reserved. Unknown During Read. Must be written as “0”.
RX1 Channel Enable
Reserved. Unknown During Read. Must be written as “0”.
RX2 Channel Enable
2
Reset Value
S Configuration and Status Registers
RSVD
24
8
0x12492
0x0
0x0
0x0
RSVD
23
7
I2SRXClkCfg
I2SGlSts
I2SGlCtrl
I2STXClkCfg
22
6
Name
21
5
20
Transmitter clock configuration
register.
Receiver clock configuration
register
I
reflects the status of the 3 RX
FIFOs and the 3 TX FIFOs.
I
4
2
2
S Global Status register. This
S Global Control register.
19
3
Description
EP93xx User’s Guide
18
2
I
17
1
2
S Controller
i2s_rx2_EN
16
21-25
0
21