EP9315-CBZ Cirrus Logic Inc, EP9315-CBZ Datasheet - Page 457

IC ARM9 SOC ENH UNIV 352PBGA

EP9315-CBZ

Manufacturer Part Number
EP9315-CBZ
Description
IC ARM9 SOC ENH UNIV 352PBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets

Specifications of EP9315-CBZ

Core Size
16/32-Bit
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, PCMCIA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
352-BGA
Controller Family/series
(ARM9)
No. Of I/o's
16
Cpu Speed
200MHz
No. Of Timers
5
Digital Ic Case Style
BGA
Supply Voltage Range
1.65V To 1.94V, 3V To 3.6V
Embedded Interface Type
SPI
Rohs Compliant
Yes
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9315A-Z
Case
BGA
Dc
06+
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1144 - KIT DEVELOPMENT EP9315 ARM9
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
 Details
Other names
598-1139

Available stocks

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Quantity
Price
Part Number:
EP9315-CBZ
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
Part Number:
EP9315-CBZ
Manufacturer:
ALTERA
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Part Number:
EP9315-CBZ
Manufacturer:
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48
HcInterruptStatus
DS785UM1
RSVD
31
15
Address:
Default:
Definition:
Bit Descriptions:
OC
30
14
29
13
28
12
0x8002_000C
0x0000_0000
Provides interrupt status information.
RSVD:
SO:
WDH:
SF:
RD:
UE:
RSVD
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
Reserved. Unknown During Read.
SchedulingOverrun. This bit is set when the USB schedule
for the current Frame overruns and after the update of
HccaFrameNumber. A scheduling overrun will also cause
the SchedulingOverrunCount of HcCommandStatus to be
incremented.
WritebackDoneHead. This bit is set immediately after HC
has written HcDoneHead to HccaDoneHead. Further
updates of the HccaDoneHead will not occur until this bit
has been cleared. HCD should only clear this bit after it
has saved the content of HccaDoneHead.
StartofFrame. This bit is set by HC at each start of a frame
and after the update of HccaFrameNumber. HC also
generates a SOF token at the same time.
ResumeDetected. This bit is set when HC detects that a
device on the USB is asserting resume signaling. It is the
transition from no resume signaling to resume signaling
causing this bit to be set. This bit is not set when HCD sets
the USBRESUME state.
UnrecoverableError. This bit is set when HC detects a
system error not related to USB. HC should not proceed
with any processing nor signaling before the system error
has been corrected. HCD clears this bit after HC has been
reset.
24
8
23
7
RSVD
RHSC
22
6
FNO
21
5
Universal Serial Bus Host Controller
UE
20
4
RD
19
3
EP93xx User’s Guide
SF
18
2
WDH
17
1
11-17
SO
16
0
11

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