EP9315-CBZ Cirrus Logic Inc, EP9315-CBZ Datasheet - Page 446

IC ARM9 SOC ENH UNIV 352PBGA

EP9315-CBZ

Manufacturer Part Number
EP9315-CBZ
Description
IC ARM9 SOC ENH UNIV 352PBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets

Specifications of EP9315-CBZ

Core Size
16/32-Bit
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, PCMCIA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
352-BGA
Controller Family/series
(ARM9)
No. Of I/o's
16
Cpu Speed
200MHz
No. Of Timers
5
Digital Ic Case Style
BGA
Supply Voltage Range
1.65V To 1.94V, 3V To 3.6V
Embedded Interface Type
SPI
Rohs Compliant
Yes
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9315A-Z
Case
BGA
Dc
06+
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1144 - KIT DEVELOPMENT EP9315 ARM9
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
 Details
Other names
598-1139

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EP9315-CBZ
Manufacturer:
Cirrus Logic Inc
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11
11-6
Universal Serial Bus Host Controller
EP93xx User’s Guide
11.2.3 Host Controller Driver Responsibilities
11.2.3.1 Host Controller Management
11.2.3.2 Bandwidth Allocation
This section summarizes the Host Controller Driver (HCD) responsibilities.
The Host Controller Driver manages the operation of the Host Controller (HC). It does so by
communicating directly to the operational registers in the Host Controller and establishing the
interrupt Endpoint Descriptor list head pointers in the HCCA.
The Host Controller Driver maintains the state of the HC, list processing pointers, list
processing enables, and interrupt enables.
All access to the USB is scheduled by the Host Controller Driver. The Host Controller Driver
allocates a portion of the available bandwidth to each periodic endpoint. If sufficient
bandwidth is not available, a newly-connected periodic endpoint will be denied access to the
bus.
Interrupt
Head
Pointers
16
24
20
12
28
18
10
26
22
14
30
17
25
21
13
29
19
11
27
23
15
31
0
8
4
2
6
1
9
5
3
7
Figure 11-5. Sample Interrupt Endpoint Schedule
32
Copyright 2007 Cirrus Logic
16
Endpoint Poll Interval (ms)
Interrupt Endpoint Descriptors
8
4
2
1
DS785UM1

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