EP9315-CBZ Cirrus Logic Inc, EP9315-CBZ Datasheet - Page 227
EP9315-CBZ
Manufacturer Part Number
EP9315-CBZ
Description
IC ARM9 SOC ENH UNIV 352PBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9315-CBZ
Core Size
16/32-Bit
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, PCMCIA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
352-BGA
Controller Family/series
(ARM9)
No. Of I/o's
16
Cpu Speed
200MHz
No. Of Timers
5
Digital Ic Case Style
BGA
Supply Voltage Range
1.65V To 1.94V, 3V To 3.6V
Embedded Interface Type
SPI
Rohs Compliant
Yes
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9315A-Z
Case
BGA
Dc
06+
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1144 - KIT DEVELOPMENT EP9315 ARM9
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1139
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP9315-CBZ
Manufacturer:
CIRRUS
Quantity:
20 000
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HClkStrtStop
DS785UM1
31
15
Address: 0x8003_001C
Default: 0x0000_0000
Definition: Horizontal Clock Active Start/Stop register
Bit Descriptions:
Note: When horizontal clock gating is required, set the STRT and STOP fields in the
30
14
RSVD
RSVD
HActiveStrtStop register to the STRT and STOP values in HClkStrtStop + 5. This is a
programming requirement that is easily overlooked.
29
13
28
12
RSVD:
STOP:
STRT:
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
Reserved - Unknown during read
Stop - Read/Write
The STOP value is the value of the Horizontal down
counter at which the HCLKEN signal becomes inactive
(stops). This indicates the end of the video clock for the
Horizontal frame. Please refer to video signalling timing
diagrams in
internal clock signal. The SPCLK output is enabled by the
logical AND of VCLKEN and HCLKEN.
Start - Read/Write
The STRT value is the value of the Horizontal down
counter at which the HCLKEN signal becomes active
(starts). This indicates the start of the video clock for the
Horizontal frame. Please refer to video signalling timing
diagrams in
internal clock signal. The SPCLK output is enabled by the
logical AND of VCLKEN and HCLKEN.
Raster Engine With Analog/LCD Integrated Timing and Interface
24
8
23
7
Figure 7-9
Figure 7-9
22
6
STOP
STRT
and
and
21
5
Figure
Figure
20
4
7-10. HCLKEN is an
7-10. HCLKEN is an
19
3
EP93xx User’s Guide
18
2
17
1
16
7-45
0
7
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