EP9315-CBZ Cirrus Logic Inc, EP9315-CBZ Datasheet - Page 708

• Manufacturer Part Number: EP9315-CBZ
• Description: IC ARM9 SOC ENH UNIV 352PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9315-CBZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, PCMCIA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 352-BGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 16
• Cpu Speed: 200MHz
• No. Of Timers: 5
• Digital Ic Case Style: BGA
• Supply Voltage Range: 1.65V To 1.94V, 3V To 3.6V
• Embedded Interface Type: SPI
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9315A-Z
• Case: BGA
• Dc: 06+
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1144 - KIT DEVELOPMENT EP9315 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1139

22
AC97IM
AC97EOI
22-20
AC’97 Controller
EP93xx User’s Guide
31
15
31
15
Address:
Definition:
Address:
30
14
30
14
29
13
29
13
28
12
28
12
0x8088_0094 - Read/Write
Controller Interrupt Enable Register. The AC’97 Controller interrupt enable
register is a read/write register that controls the interrupt enables for the
interrupts outside the FIFO channels.
Bit Descriptions:
RSVD:
SLOT2TXCOMPLETE:If this bit is set to “1”, the SLOT2TXCOMPLETE
CODECREADY:
WINT:
GPIOINT:
GPIOTXCOMPLETE:If this bit is set to “1”, the GPIOTXCOMPLETE interrupt
SLOT2RXVALID: If this bit is set to “1”, SLOT2RXVALID interrupt is enabled.
SLOT1TXCOMPLETE:If this bit is set to “1”, SLOT1TXCOMPLETE interrupt is
0x8088_0098 - Write Only
RSVD
27
11
27
11
26
10
26
10
25
9
Copyright 2007 Cirrus Logic
25
9
RSVD
Reserved. Unknown During Read.
If this bit is set to “1”, the Codec Ready Interrupt is
If this bit is set to “1”, the Wake-up Interrupt is enabled.
If this bit is set to “1”, the GPIO interrupt is enabled.
24
8
24
8
interrupt is enabled.
enabled.
is enabled.
enabled.
23
7
RSVD
23
7
COMPLETE
SLOT2TX
22
6
22
6
CODEC
READY
21
5
21
5
WINT
20
4
20
4
GPIO
INT
19
3
19
3
COMPLETE
GPIOTX
18
18
2
2
CODECREADY
SLOT2RX
VALID
17
17
1
1
DS785UM1
COMPLETE
SLOT1TX
WINT
16
0
16
0