EP9315-CBZ Cirrus Logic Inc, EP9315-CBZ Datasheet - Page 402
EP9315-CBZ
Manufacturer Part Number
EP9315-CBZ
Description
IC ARM9 SOC ENH UNIV 352PBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9315-CBZ
Core Size
16/32-Bit
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, PCMCIA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
352-BGA
Controller Family/series
(ARM9)
No. Of I/o's
16
Cpu Speed
200MHz
No. Of Timers
5
Digital Ic Case Style
BGA
Supply Voltage Range
1.65V To 1.94V, 3V To 3.6V
Embedded Interface Type
SPI
Rohs Compliant
Yes
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9315A-Z
Case
BGA
Dc
06+
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1144 - KIT DEVELOPMENT EP9315 ARM9
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1139
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP9315-CBZ
Manufacturer:
CIRRUS
Quantity:
20 000
- Current page: 402 of 824
- Download datasheet (13Mb)
10
10-8
10.1.9.1.1 DMA_IDLE
10.1.9.1.2 DMA_STALL
10.1.9.1.3 DMA_ON
10.1.9.1.4 DMA_NEXT
DMA Controller
EP93xx User’s Guide
The DMA Channel FSM always resets to the DMA_IDLE state.
The DMA Channel FSM always enters the DMA_IDLE state when the channel is disabled
(CONTROL[4]).
The DMA Channel FSM enters the DMA_STALL state when the channel enabled, no STALL
interrupt is generated for this condition.
The DMA Channel FSM enters the DMA_STALL state if a memory buffer completes in the
ON state. A DMA_STALL interrupt is generated for this condition.
The DMA Channel FSM enters the DMA_STALL state and terminates the current memory
buffer if there is a peripheral error (TxEnd/RxEnd indication) while in the DMA_ON state, and
ICE is not active.
The DMA Channel FSM enters the DMA_STALL state and terminates the current memory
buffer if there is a peripheral error (TxEnd/RxEnd indication) while in the DMA_NEXT state,
and ABORT is active, and ICE inactive. No STALL interrupt is generated for this condition.
No data transfers occur in this state.
The DMA Channel FSM enters this state when a base address is written in the stall state.
Data transfers occur in this state.
The DMA Channel FSM enters this state when the current memory buffer expires, or when a
peripheral error occurs that does not cause an abort, while in the DMA_NEXT state. The
transition from DMA_NEXT to DMA_ON state results in a NFB interrupt being generated.
The DMA Channel FSM enters this state when a base address register is written in the
DMA_ON state (that is, for buffer Y). The DMA will continue to transfer using the buffer (that
is, buffer X) that it began with in the DMA_ON state. When buffer X expires or when a
peripheral error occurs, then the DMA will automatically switch over to using the next buffer
(buffer Y). It will generate an interrupt (NFBint) to signal to the processor that it is switching
over to a new buffer and that the old buffer descriptor (buffer X) is available to be updated.
Data transfers occur in this state.
CE:
ICE:
ABORT:
Copyright 2007 Cirrus Logic
Channel (Peripheral) Error
CONTROL[6] - Ignore Channel Error. This bit may be set
for data streams whereby the end user can tolerate
occasional bit errors. If it is not set then the DMA will abort
its transfer in receipt of a peripheral error.
CONTROL[5]
DS785UM1
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