EP9315-CBZ Cirrus Logic Inc, EP9315-CBZ Datasheet - Page 437
EP9315-CBZ
Manufacturer Part Number
EP9315-CBZ
Description
IC ARM9 SOC ENH UNIV 352PBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9315-CBZ
Core Size
16/32-Bit
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, PCMCIA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
352-BGA
Controller Family/series
(ARM9)
No. Of I/o's
16
Cpu Speed
200MHz
No. Of Timers
5
Digital Ic Case Style
BGA
Supply Voltage Range
1.65V To 1.94V, 3V To 3.6V
Embedded Interface Type
SPI
Rohs Compliant
Yes
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9315A-Z
Case
BGA
Dc
06+
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1144 - KIT DEVELOPMENT EP9315 ARM9
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1139
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP9315-CBZ
Manufacturer:
CIRRUS
Quantity:
20 000
- Current page: 437 of 824
- Download datasheet (13Mb)
DAR_BASEx
SAR_CURRENTx
DS785UM1
31
15
31
15
Address:
Definition:
Bit Descriptions:
Address:
Definition:
30
14
30
14
29
13
29
13
28
12
28
12
DAR_BASE0: Channel Base Address + 0x002C- Read/Write
DAR_BASE1: Channel Base Address + 0x0030 - Read/Write
This register contains the base memory address to which the DMA controller
transfers data.
DAR_BASEx:
SAR_CURRENT0: Channel Base Address + 0x0024 - Read Only
SAR_CURRENT1: Channel Base Address + 0x0028 - Read Only
This is the Channel Current Source Address Register.
27
11
27
11
26
10
26
10
Copyright 2007 Cirrus Logic
25
25
9
9
x = 0 or 1 representing the double buffer per channel. This
register contains the base memory address to which the
DMA controller sends data. At least 1 of the DAR_BASEx
registers must be programmed before the ENABLE bit and
the START bit (in the case of software trigger M2M mode)
are set in the Control register, and also before the
corresponding BCRx register is programmed. The second
buffer descriptor can be programmed while the transfer
using the ‘other’ buffer is being carried out (thus reducing
software latency impact). When transferring from memory
to external peripheral, the DAR_BASEx will contain the
base address of the memory mapped device.
SAR_CURRENTx
SAR_CURRENTx
DAR_BASEx
DAR_BASEx
24
24
8
8
23
23
7
7
22
22
6
6
21
21
5
5
20
20
4
4
19
19
3
3
EP93xx User’s Guide
18
18
2
2
DMA Controller
17
17
1
1
10-43
16
16
0
0
10
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