EP9315-CBZ Cirrus Logic Inc, EP9315-CBZ Datasheet - Page 494
EP9315-CBZ
Manufacturer Part Number
EP9315-CBZ
Description
IC ARM9 SOC ENH UNIV 352PBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9315-CBZ
Core Size
16/32-Bit
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, PCMCIA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
352-BGA
Controller Family/series
(ARM9)
No. Of I/o's
16
Cpu Speed
200MHz
No. Of Timers
5
Digital Ic Case Style
BGA
Supply Voltage Range
1.65V To 1.94V, 3V To 3.6V
Embedded Interface Type
SPI
Rohs Compliant
Yes
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9315A-Z
Case
BGA
Dc
06+
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1144 - KIT DEVELOPMENT EP9315 ARM9
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1139
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP9315-CBZ
Manufacturer:
CIRRUS
Quantity:
20 000
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12
PCMCIACtrl
12-16
Static Memory Controller
EP93xx User’s Guide
31
15
Address: 0x8008_0040 - Read/Write
Default: 0x0000_0000
Definition: PC Card Control register
Bit Descriptions:
30
14
29
13
28
12
AI:
HI:
PI:
RSVD:
27
11
RSVD
26
10
Copyright 2007 Cirrus Logic
25
9
0 - 8-bit wide Common space
1 - 16-bit wide Common space
IO Space Access time - Read/Write
The value written to this field specifies the minimum
‘number of HCLK cycles, minus 1’ that the data strobe,
MCDAENn
The data strobe assertion time is specified by (AI+1)
HCLK cycles. For example, if AI = 0x10, the data strobe
assertion time is 16 + 1 = 17 cycles of HCLK
IO space Hold time - Read/Write
The value written to this field specifies the minimum
‘number of HCLK cycles, minus 1’ between de-asserting
the data strobe, MCDAENn
strobe, MCADENn.
The Hold time is specified by (HI +1) HCLK cycles. For
example, if HI = 0xC, the Hold time is 12 + 1 = 13 cycles of
HCLK.
IO space setup time - Read/Write
The value written to this field specifies the ‘number of
HCLK cycles, minus 1’ that the address strobe,
MCADENn, is set up before assertion of the data strobe,
MCDAENn.
The Setup time is specified by (PI+1) HCLK cycles. For
example, if PI = 0x25, the Setup time is 37 + 1 = 38 cycles
of HCLK.
Reserved - Unknown During Read
24
8
RSVD
,
23
7
is asserted during a Read or Write access.
22
6
21
5
,
and de-asserting the address
WEN
20
4
RSVD
19
3
PCRST
18
2
RSVD
17
1
DS785UM1
PCEN
16
0
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