EP9315-CBZ Cirrus Logic Inc, EP9315-CBZ Datasheet - Page 19
EP9315-CBZ
Manufacturer Part Number
EP9315-CBZ
Description
IC ARM9 SOC ENH UNIV 352PBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9315-CBZ
Core Size
16/32-Bit
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, PCMCIA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
352-BGA
Controller Family/series
(ARM9)
No. Of I/o's
16
Cpu Speed
200MHz
No. Of Timers
5
Digital Ic Case Style
BGA
Supply Voltage Range
1.65V To 1.94V, 3V To 3.6V
Embedded Interface Type
SPI
Rohs Compliant
Yes
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9315A-Z
Case
BGA
Dc
06+
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1144 - KIT DEVELOPMENT EP9315 ARM9
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1139
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP9315-CBZ
Manufacturer:
CIRRUS
Quantity:
20 000
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EP93xx User’s Guide
Table 8-2. bpp Memory Organization............................................................................................................8-5
Table 8-3. 4 bpp Memory Organization.........................................................................................................8-5
Table 8-4. 8 bpp Memory Organization.........................................................................................................8-6
Table 8-5. 16 bpp Memory Organization.......................................................................................................8-6
Table 8-6. 24 bpp Packed Memory Organization (4 pixel/ 3 words) .............................................................8-7
Table 8-7. 24 bpp Unpacked Memory Organization (1 pixel/ 1 word) ...........................................................8-7
Table 8-8. Transfer Example 1......................................................................................................................8-8
Table 8-9. Transfer Example 2......................................................................................................................8-9
Table 8-10. Transfer Example 3....................................................................................................................8-9
Table 8-11. Transfer Example 4....................................................................................................................8-9
Table 8-12. Transfer Example 5....................................................................................................................8-9
Table 8-13. 4 BPP Memory Layout for Source Image.................................................................................8-10
Table 8-14. 4 BPP Memory Layout for Destination Image ..........................................................................8-10
Table 8-15. 8 BPP Memory Layout for Source Image.................................................................................8-11
Table 8-16. 8 BPP Memory Layout for Destination Image ..........................................................................8-11
Table 8-17. 16 BPP Memory Layout for Source Image...............................................................................8-11
Table 8-18. 16 BPP Memory Layout for Destination Image ........................................................................8-12
Table 8-19. 24 BPP Memory Layout for Source Image...............................................................................8-12
Table 8-20. 24 BPP Memory Layout for Destination Image .......................................................................8-13
Table 8-21. Words Needed for Six 24-Bit Pixels .........................................................................................8-19
Table 8-22. Graphics Accelerator Registers ...............................................................................................8-22
Table 8-23. Pixel Mode Encoding ...............................................................................................................8-30
Table 9-1. FIFO RAM Address Map..............................................................................................................9-3
Table 9-2. RXCtl.MA and RXCtl.IAHA[0] Relationships ..............................................................................9-10
Table 9-3. Ethernet Register List.................................................................................................................9-40
Table 9-4. Individual Accept, RxFlow Control Enable and Pause Accept Bits ............................................9-42
Table 9-5. Address Filter Pointer.................................................................................................................9-52
Table 10-1. Data Transfer Size .................................................................................................................10-18
Table 10-2. M2P DMA Bus Arbitration ......................................................................................................10-19
Table 10-3. DMA Memory Map .................................................................................................................10-20
Table 10-4. Internal M2P/P2M Channel Register Map..............................................................................10-21
Table 10-5. PPALLOC Register Bits Decode for a Transmit Channel ......................................................10-24
Table 10-6. PPALLOC Register Bits Decode for a Receive Channel .......................................................10-24
Table 10-7. PPALLOC Register Reset Values..........................................................................................10-24
Table 10-8. PPALLOC Register Reset Values..........................................................................................10-30
Table 10-9. BWC Decode Values .............................................................................................................10-33
Table 10-10. DMA Global Interrupt (DMAGlInt) Register ..........................................................................10-45
©
DS785UM1
Copyright 2007 Cirrus Logic, Inc.
xix
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