EP9315-CBZ Cirrus Logic Inc, EP9315-CBZ Datasheet - Page 444

• Manufacturer Part Number: EP9315-CBZ
• Description: IC ARM9 SOC ENH UNIV 352PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9315-CBZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, PCMCIA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 352-BGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 16
• Cpu Speed: 200MHz
• No. Of Timers: 5
• Digital Ic Case Style: BGA
• Supply Voltage Range: 1.65V To 1.94V, 3V To 3.6V
• Embedded Interface Type: SPI
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9315A-Z
• Case: BGA
• Dc: 06+
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1144 - KIT DEVELOPMENT EP9315 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1139

11
11-4
Universal Serial Bus Host Controller
EP93xx User’s Guide
11.2.2.2 Data Structures
The basic building blocks for communication across the interface are the Endpoint Descriptor
(ED) and Transfer Descriptor (TD).
The Host Controller Driver assigns an Endpoint Descriptor to each endpoint in the system.
The Endpoint Descriptor contains the information necessary for the Host Controller to
communicate with the endpoint. The fields include the maximum packet size, the endpoint
address, the speed of the endpoint, and the direction of data flow. Endpoint Descriptors are
linked in a list.
A queue of Transfer Descriptors is linked to the Endpoint Descriptor for the specific endpoint.
The Transfer Descriptor contains the information necessary to describe the data packets to
be transferred. The fields include data toggle information, shared memory buffer location, and
completion status codes. Each Transfer Descriptor contains information that describes one or
more data packets. The data buffer for each Transfer Descriptor ranges in size from 0 to 8192
bytes with a maximum of one physical page crossing. Transfer Descriptors are linked in a
queue: the first one queued is the first one processed.
Each data transfer type has its own linked list of Endpoint Descriptors to be processed.
Figure
The head pointers to the bulk and control Endpoint Descriptor lists are maintained within the
operational registers in the HC. The Host Controller Driver initializes these pointers prior to
the Host Controller gaining access to them. Should these pointers need to be updated, the
Host Controller Driver may need to halt the Host Controller from processing the specific list,
update the pointer, then re-enable the HC.
The head pointers to the interrupt Endpoint Descriptor lists are maintained within the HCCA.
There is no separate head pointer for isochronous transfers. The first isochronous Endpoint
Descriptor simply links to the last interrupt Endpoint Descriptor. There are 32 interrupt head
pointers. The head pointer used for a particular frame is determined by using the last 5 bits of
the Frame Counter as an offset into the interrupt array within the HCCA.
The interrupt Endpoint Descriptors are organized into a tree structure with the head pointers
being the leaf nodes. The desired polling rate of an Interrupt Endpoint is achieved by
11-3, Typical List Structure, is a representation of the data structure relationships.
Head Ptr
Figure 11-3. Typical List Structure
ED
TD
TD
TD
Copyright 2007 Cirrus Logic
ED
TD
ED
TD
TD
ED
TD
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