AT90PWM81-16SN Atmel, AT90PWM81-16SN Datasheet - Page 104

IC MCU AVR 8K FLASH ISP 20SOIC

AT90PWM81-16SN

Manufacturer Part Number
AT90PWM81-16SN
Description
IC MCU AVR 8K FLASH ISP 20SOIC
Manufacturer
Atmel
Series
AVR® 90PWM Lightingr
Datasheet

Specifications of AT90PWM81-16SN

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI
Peripherals
Brown-out Detect/Reset, PWM, WDT
Number Of I /o
16
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
20-SOIC (7.5mm Width)
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
SPI
Maximum Clock Frequency
16 MHz
Number Of Timers
1
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
On-chip Dac
10 bit, 1 Channel
Height
2.35 mm
Length
13 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.7 V
Width
7.6 mm
For Use With
ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT90PWM81-16SN
Manufacturer:
Atmel
Quantity:
1 500
12.5
12.5.1
104
Functional Description
AT90PWM81
Waveform Cycles
Note:
The waveform generated by PSC can be described as a sequence of two waveforms.
The first waveform is relative to PSCOUTn0 output and part A of PSC. The part of this waveform is sub-
cycle A in the following figure.
The second waveform is relative to PSCOUTn1 output and part B of PSC. The part of this waveform is
sub-cycle B in the following figure.
The complete waveform is ended with the end of sub-cycle B. It means at the end of waveform B.
Figure 12-4.
Figure 12-5.
Ramps illustrate the output of the PSC counter included in the waveform generators. Centered Mode is
like a one ramp mode which count down up and down.
Notice that the update of a new set of values is done regardless of ramp Mode at the top of the last ramp.
4 Ramp Mode
2 Ramp Mode
1 Ramp Mode
Centered Mode
1. See
2.
Ramp A0
See “Analog Synchronization” on page 130.
Cycle Presentation in 1, 2 & 4 Ramp Mode
Cycle Presentation in Centered Mode
Figure 12-41 on page 131
Sub-Cycle A
Ramp A
Ramp A1
PSC Cycle
Ramp B0
Sub-Cycle B
Ramp B
Ramp B1
PSC Cycle
UPDATE
UPDATE
7734P–AVR–08/10

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