AT90PWM81-16SN Atmel, AT90PWM81-16SN Datasheet - Page 173

• Manufacturer Part Number: AT90PWM81-16SN
• Description: IC MCU AVR 8K FLASH ISP 20SOIC
• Manufacturer: Atmel
• Series: AVR® 90PWM Lightingr

Specifications of AT90PWM81-16SN

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI
• Peripherals: Brown-out Detect/Reset, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 20-SOIC (7.5mm Width)
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI
• Maximum Clock Frequency: 16 MHz
• Number Of Timers: 1
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 1 Channel
• Height: 2.35 mm
• Length: 13 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 7.6 mm
• For Use With: ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.23.5
13.23.6
7734P–AVR–08/10
Output Compare RB Register – OCR0RBH and OCR0RBL
PSCR Configuration Register – PCNF0
The Output Compare Registers RA, RB, SA and SB contain a 12-bit value that is continuously compared
with the PSCR counter value. A match can be used to generate an Output Compare interrupt, or to gener-
ate a waveform output on the associated pin.
The Output Compare Registers RB contains also a 4-bit value that is used for the flank width modulation.
The Output Compare Registers are 12-bit in size. To ensure that both the high and low bytes are written
simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary
high byte register (TEMP). This temporary register is shared by all the other 16-bit registers.
• Bit 7 - PFIFTY0: PSCR Fifty
Writing this bit to one, set the PSCR in a fifty percent mode where only OCR0RBH/L and OCR0SBH/L
are used. They are duplicated in OCR0RAH/L and OCR0SAH/L during the update of OCR0RBH/L. This
feature is useful to perform fifty percent waveforms.
• Bit 6 - PALOCK0: PSCR Autolock
When this bit is set, the Output Compare Registers RA, SA, SB, the Output Matrix POM2 and the PSCR
Output Configuration PSOC0 can be written without disturbing the PSCR cycles. The update of the PSCR
internal registers will be done at the end of the PSCR cycle if the Output Compare Register RB has been
the last written.
When set, this bit prevails over LOCK (bit 5)
• Bit 5 – PLOCK0: PSCR Lock
When this bit is set, the Output Compare Registers RA, RB, SA, SB, the Output Matrix POM2 and the
PSCR Output Configuration PSOC0 can be written without disturbing the PSCR cycles. The update of the
PSCR internal registers will be done if the LOCK bit is released to zero.
• Bit 4:3 – PMODE01: 0: PSCR Mode
Select the mode of PSC.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
7
PFIFTY0
R/W
0
7
OCR0RB[15:12]
OCR0RB[7:0]
W
0
6
W
0
6
PALOCK0 PLOCK0
R/W
0
5
W
0
5
R/W
0
0
4
PMODE01 PMODE00 POP0
R/W
0
4
W
3
R/W
0
3
OCR0RB[11:8]
W
0
2
R/W
0
2
W
0
1
PCLKSEL0 -
R/W
0
1
W
0
AT90PWM81
0
R/W
0
0
W
0
PCNF0
OCR0RBH
OCR0RBL
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