AT90PWM81-16SN Atmel, AT90PWM81-16SN Datasheet - Page 159
AT90PWM81-16SN
Manufacturer Part Number
AT90PWM81-16SN
Description
IC MCU AVR 8K FLASH ISP 20SOIC
Manufacturer
Atmel
Series
AVR® 90PWM Lightingr
Datasheet
1.AT90PWM81-16MN.pdf
(325 pages)
Specifications of AT90PWM81-16SN
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI
Peripherals
Brown-out Detect/Reset, PWM, WDT
Number Of I /o
16
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
20-SOIC (7.5mm Width)
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
SPI
Maximum Clock Frequency
16 MHz
Number Of Timers
1
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
On-chip Dac
10 bit, 1 Channel
Height
2.35 mm
Length
13 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.7 V
Width
7.6 mm
For Use With
ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT90PWM81-16SN
Manufacturer:
Atmel
Quantity:
1 500
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13.8.4
13.8.4.1
13.8.4.2
7734P–AVR–08/10
PSCR Input Configuration
Filter Enable
Signal Polarity
Figure 13-13. Burst Generation
The PSCR Input Configuration is done by programming bits in configuration registers.
If the “Filter Enable” bit is set, a digital filter of 4 cycles is inserted before evaluation of the signal. The
disable of this function is mainly needed for prescaled PSCR clock sources, where the noise cancellation
gives too high latency.
Important: If the digital filter is active, the level sensitivity is true also with a disturbed PSCR clock to
deactivate the outputs (emergency protection of external component). Likewise when used as fault input,
PSCr Input A or Input B have to go through PSCR to act on PSCOUTr0/1/2/3 output. This way needs that
CLK
can deactivate directly the PSCR output. Notice that in this case, input is still taken into account as usually
by Input Module System as soon as CLK
PSCR Input Flittering
One can select the active edge (edge modes) or the active level (level modes) See PELEV0x bit descrip-
tion in Section “PSCR Input A Control Register – PFRC0A”, page 17513.23.8.
PSCOUTn0
PSCOUTn1
PSCn Input A
(high level)
PSCn Input A
(low level)
PSCR
is running. So thanks to PSCR Asynchronous Output Control bit (PAOCrA/B), PSCrIN0/1 input
PSC Input
Module X
CLK
PSC
OFF
Digital
Filter
4 x CLK
PSCR
PSC
is running.
BURST
Ouput
Stage
PSCn Input A or B
PSCOUTnX
PIN
AT90PWM81
159
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