AT90PWM81-16SN Atmel, AT90PWM81-16SN Datasheet - Page 162

• Manufacturer Part Number: AT90PWM81-16SN
• Description: IC MCU AVR 8K FLASH ISP 20SOIC
• Manufacturer: Atmel
• Series: AVR® 90PWM Lightingr

Specifications of AT90PWM81-16SN

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI
• Peripherals: Brown-out Detect/Reset, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 20-SOIC (7.5mm Width)
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI
• Maximum Clock Frequency: 16 MHz
• Number Of Timers: 1
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 1 Channel
• Height: 2.35 mm
• Length: 13 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 7.6 mm
• For Use With: ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.10 PSCR Input Mode 2: Stop signal, Execute Opposite Dead-Time and Wait
162
PSCOUTn0
PSCOUTn1
PSC Input A
PSC Input B
PSCOUTn0
PSCOUTn1
PSC Input A
PSC Input B
AT90PWM81
DT0
DT0
OT0
OT0
Figure 13-16. PSCr behavior versus PSCr Input A in Fault Mode 2
PSCR Input A is take into account during DT0 and OT0 only. It has no effect during DT1 and OT1.
When PSCr Input A event occurs, PSCR releases PSCOUTr0, jumps and executes DT1 plus OT1 and then
waits for PSCR Input A inactive state.
Even if PSCR Input A is released during DT1 or OT1, DT1 plus OT1 sub-cycle is always completely
executed.
Figure 13-17. PSCr behavior versus PSCr Input B in Fault Mode 2
PSCR Input B is take into account during DT1 and OT1 only. It has no effect during DT0 and OT0.
When PSCR Input B event occurs, PSCR releases PSCOUTr1, jumps and executes DT0 plus OT0 and
then waits for PSCR Input B inactive state.
Even if PSCR Input B is released during DT0 or OT0, DT0 plus OT0 sub-cycle is always completely
executed.
DT1
DT1
OT1
OT1
DT0
DT0 OT0 DT1
OT0
DT1
OT1
OT1
DT0
OT0
DT0
OT0
DT1
DT1
7734P–AVR–08/10
OT1
OT1