AT90PWM81-16SN Atmel, AT90PWM81-16SN Datasheet - Page 140

• Manufacturer Part Number: AT90PWM81-16SN
• Description: IC MCU AVR 8K FLASH ISP 20SOIC
• Manufacturer: Atmel
• Series: AVR® 90PWM Lightingr

Specifications of AT90PWM81-16SN

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI
• Peripherals: Brown-out Detect/Reset, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 20-SOIC (7.5mm Width)
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI
• Maximum Clock Frequency: 16 MHz
• Number Of Timers: 1
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 1 Channel
• Height: 2.35 mm
• Length: 13 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 7.6 mm
• For Use With: ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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12.25.11
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AT90PWM81
PSC n Input A Control Register – PFRCnA
PSC n Input B Control Register – PFRCnB
Table 12-20.
• Bit 5 – PBFMn0 : Balance Flank Width Modulation bit 0
Defines the Flank Width Modulation, together with PBFMn1 bit in PCNFEn register.
See
• Bit 4 – PAOCnB : PSC n Asynchronous Output Control B
When this bit is set, Fault input selected to block B can act directly to PSCOUTn1 and PSCOUT23 out-
puts. See Section “PSC Clock Sources”, page 132.
• Bit 3 – PAOCnA : PSC n Asynchronous Output Control A
When this bit is set, Fault input selected to block A can act directly to PSCOUTn0 and PSCOUT22 out-
puts. See Section “PSC Clock Sources”, page 132.
• Bit 2 – PARUNn : PSC n Autorun
When this bit is set, the PSC n starts with PSCn-1. That means that PSC n starts :
• Bit 1 – PCCYCn : PSC n Complete Cycle
When this bit is set, the PSC n completes the entire waveform cycle before halt operation requested by
clearing PRUNn. This bit is not relevant in slave mode (PARUNn = 1).
• Bit 0 – PRUNn : PSC n Run
Writing this bit to one starts the PSC n.
When set, this bit prevails over PARUNn bit.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
PPREn1
0
1
1
• when PRUNn bit in PCTLn register is set,
• or when PARUNn bit in PCTLn is set and PRUNn-1 bit in PCTLn-1 register is set (or PARUN0 bit
and PRUN0).
Table 12-15 on page 137
7
PCAEnA
R/W
0
7
PCAEnB
R/W
0
PSC n Prescaler Selection
PPREn0
1
0
1
6
PISELnA0 PELEVnA0 PFLTEnA
R/W
0
6
PISELnB0 PELEVnB0 PFLTEnB
R/W
0
Description
Divide the PSC input clock by 4
Divide the PSC input clock by 16
Divide the PSC clock by 64
5
R/W
0
5
R/W
0
4
R/W
0
4
R/W
0
3
PRFMnA3 PRFMnA2 PRFMnA1 PRFMnA0 PFRCnA
0
3
PRFMnB3 PRFMnB2 PRFMnB1 PRFMnB0 PFRCnB
0
R/W
R/W
2
R/W
0
2
R/W
0
1
R/W
0
1
R/W
0
0
R/W
0
0
R/W
0
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