AT90PWM81-16SN Atmel, AT90PWM81-16SN Datasheet - Page 206

• Manufacturer Part Number: AT90PWM81-16SN
• Description: IC MCU AVR 8K FLASH ISP 20SOIC
• Manufacturer: Atmel
• Series: AVR® 90PWM Lightingr

Specifications of AT90PWM81-16SN

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI
• Peripherals: Brown-out Detect/Reset, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 20-SOIC (7.5mm Width)
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI
• Maximum Clock Frequency: 16 MHz
• Number Of Timers: 1
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 1 Channel
• Height: 2.35 mm
• Length: 13 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 7.6 mm
• For Use With: ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.4
206
Prescaling and Conversion Timing
AT90PWM81
Figure 17-2.
Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon as the
ongoing conversion has finished. The ADC then operates in Free Running mode, constantly sampling and
updating the ADC Data Register. The first conversion must be started by writing a logical one to the
ADSC bit in ADCSRA. In this mode the ADC will perform successive conversions independently of
whether the ADC Interrupt Flag, ADIF is cleared or not. The free running mode is not allowed on the
amplified channels.
If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA to one.
ADSC can also be used to determine if a conversion is in progress. The ADSC bit will be read as one dur-
ing a conversion, independently of how the conversion was started.
Figure 17-3.
By default, the successive approximation circuitry requires an input clock frequency between 50 kHz and
2 MHz to get maximum resolution. If a lower resolution than 10 bits is needed, the input clock frequency
to the ADC can be higher than 2 MHz to get a higher sample rate.
The ADC module contains a prescaler, which generates an acceptable ADC clock frequency from any
CPU frequency above 100 kHz. The prescaling is set by the ADPS bits in ADCSRA. The prescaler starts
counting from the moment the ADC is switched on by setting the ADEN bit in ADCSRA. The prescaler
keeps running for as long as the ADEN bit is set, and is continuously reset when ADEN is low.
ADC Auto Trigger Logic
ADC Prescaler
ADSC
SOURCE n
ADIF
SOURCE 1
.
.
.
.
ADEN
START
ADTS[2:0]
ADPS0
ADPS1
ADPS2
CK
DETECTOR
EDGE
Reset
ADATE
7-BIT ADC PRESCALER
ADC CLOCK SOURCE
START
CONVERSION
PRESCALER
LOGIC
CLK
ADC
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