AT90PWM81-16SN Atmel, AT90PWM81-16SN Datasheet - Page 12

• Manufacturer Part Number: AT90PWM81-16SN
• Description: IC MCU AVR 8K FLASH ISP 20SOIC
• Manufacturer: Atmel
• Series: AVR® 90PWM Lightingr

Specifications of AT90PWM81-16SN

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI
• Peripherals: Brown-out Detect/Reset, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 20-SOIC (7.5mm Width)
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI
• Maximum Clock Frequency: 16 MHz
• Number Of Timers: 1
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 1 Channel
• Height: 2.35 mm
• Length: 13 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 7.6 mm
• For Use With: ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.6
3.7
12
Stack Pointer
Instruction Execution Timing
AT90PWM81
In the different addressing modes these address registers have functions as fixed displacement, automatic
increment, and automatic decrement (see the instruction set reference for details).
The Stack is mainly used for storing temporary data, for storing local variables and for storing return
addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the
Stack. Note that the Stack is implemented as growing from higher memory locations to lower memory
locations. This implies that a Stack PUSH command decreases the Stack Pointer.
The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are
located. This Stack space in the data SRAM must be defined by the program before any subroutine calls
are executed or interrupts are enabled. The Stack Pointer must be set to point above 0x100. The Stack
Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is
decremented by two when the return address is pushed onto the Stack with subroutine call or interrupt.
The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction,
and it is incremented by two when data is popped from the Stack with return from subroutine RET or
return from interrupt RETI.
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually
used is implementation dependent. Note that the data space in some implementations of the AVR architec-
ture is so small that only SPL is needed. In this case, the SPH Register will not be present.
This section describes the general access timing concepts for instruction execution. The AVR CPU is
driven by the CPU clock clk
clock division is used.
Figure 3-4
tecture and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1
MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and
functions per power-unit.
Bit
Read/Write
Initial Value
Y-register
Z-register
shows the parallel instruction fetches and instruction executions enabled by the Harvard archi-
15
SP15
SP7
7
R/W
R/W
0
0
7
R29 (0x1D)
15
7
R31 (0x1F)
14
SP14
SP6
6
R/W
R/W
0
0
CPU
, directly generated from the selected clock source for the chip. No internal
13
SP13
SP5
5
R/W
R/W
0
0
ZH
0
12
SP12
SP4
4
R/W
R/W
0
0
11
SP11
SP3
3
R/W
R/W
0
0
0
7
R28 (0x1C)
7
R30 (0x1E)
10
SP10
SP2
2
R/W
R/W
0
0
9
SP9
SP1
1
R/W
R/W
0
0
ZL
8
SP8
SP0
0
R/W
R/W
0
0
0
SPH
SPL
7734P–AVR–08/10
0
0