AT90PWM81-16SN Atmel, AT90PWM81-16SN Datasheet - Page 118

• Manufacturer Part Number: AT90PWM81-16SN
• Description: IC MCU AVR 8K FLASH ISP 20SOIC
• Manufacturer: Atmel
• Series: AVR® 90PWM Lightingr

Specifications of AT90PWM81-16SN

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI
• Peripherals: Brown-out Detect/Reset, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 20-SOIC (7.5mm Width)
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI
• Maximum Clock Frequency: 16 MHz
• Number Of Timers: 1
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 1 Channel
• Height: 2.35 mm
• Length: 13 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 7.6 mm
• For Use With: ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.8.4
12.8.4.1
12.8.4.2
118
AT90PWM81
PSC Input Configuration
Filter Enable
Signal Polarity
Figure 12-20. Burst Generation
The PSC Input Configuration is done by programming bits in configuration registers.
If the “Filter Enable” bit is set, a digital filter of 4 cycles is inserted before evaluation of the signal. The
disable of this function is mainly needed for prescaled PSC clock sources, where the noise cancellation
gives too high latency.
Important: If the digital filter is active, the level sensitivity is true also with a disturbed PSC clock to deac-
tivate the outputs (emergency protection of external component). Likewise when used as fault input, PSCn
Input A or Input B have to go through PSC to act on PSCOUTn0/1/2/3 output. This way needs that
CLK
can deactivate directly the PSC output. Notice that in this case, input is still taken into account as usually
by Input Module System as soon as CLK
Figure 12-21. PSC Input Flittering
One can select the active edge (edge modes) or the active level (level modes) See PELEVnx bit descrip-
tion in Section “PSC n Input A Control Register – PFRCnA”, page 14012.25.10.
PSCOUTn0
PSCOUTn1
PSCn Input A
(high level)
PSCn Input A
(low level)
PSC
is running. So thanks to PSC Asynchronous Output Control bit (PAOCnA/B), PSCnIN0/1 input
PSC Input
Module X
CLK
PSC
OFF
Digital
Filter
4 x CLK
PSC
PSC
is running.
BURST
Ouput
Stage
PSCn Input A or B
PSCOUTnX
PIN
7734P–AVR–08/10