AT90PWM81-16SN Atmel, AT90PWM81-16SN Datasheet - Page 93

• Manufacturer Part Number: AT90PWM81-16SN
• Description: IC MCU AVR 8K FLASH ISP 20SOIC
• Manufacturer: Atmel
• Series: AVR® 90PWM Lightingr

Specifications of AT90PWM81-16SN

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI
• Peripherals: Brown-out Detect/Reset, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 20-SOIC (7.5mm Width)
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI
• Maximum Clock Frequency: 16 MHz
• Number Of Timers: 1
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 1 Channel
• Height: 2.35 mm
• Length: 13 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 7.6 mm
• For Use With: ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.5.2
11.5.3
11.6
11.6.1
7734P–AVR–08/10
Modes of Operation
Noise Canceler
Using the Input Capture Unit
Normal Mode
Both the Input Capture pin (ICP1) and the Analog Comparator 1 output (AC1O) inputs are sampled using
the same technique as for the T1 pin
However, when the noise canceler is enabled, additional logic is inserted before the edge detector, which
increases the delay by four system clock cycles. Note that the input of the noise canceler and edge detector
is always enabled unless the Timer/Counter is set in a Waveform Generation mode that uses ICR1 to
define TOP.
An Input Capture can be triggered by software by controlling the port of the ICP1 pin.
The noise canceler improves noise immunity by using a simple digital filtering scheme. The noise can-
celer input is monitored over four samples, and all four must be equal for changing the output that in turn
is used by the edge detector.
The noise canceler is enabled by setting the Input Capture Noise Canceler (ICNC1) bit in Timer/Counter
Control Register B (TCCR1B). When enabled the noise canceler introduces additional four system clock
cycles of delay from a change applied to the input, to the update of the ICR1 Register. The noise canceler
uses the system clock and is therefore not affected by the prescaler.
The main challenge when using the Input Capture unit is to assign enough processor capacity for handling
the incoming events. The time between two events is critical. If the processor has not read the captured
value in the ICR1 Register before the next event occurs, the ICR1 will be overwritten with a new value. In
this case the result of the capture will be incorrect.
When using the Input Capture interrupt, the ICR1 Register should be read as early in the interrupt handler
routine as possible. Even though the Input Capture interrupt has relatively high priority, the maximum
interrupt response time is dependent on the maximum number of clock cycles it takes to handle any of the
other interrupt requests.
Using the Input Capture unit in any mode of operation when the TOP value (resolution) is actively
changed during operation, is not recommended.
Measurement of an external signal’s duty cycle requires that the trigger edge is changed after each cap-
ture. Changing the edge sensing must be done as early as possible after the ICR1 Register has been read.
After a change of the edge, the Input Capture Flag (ICF1) must be cleared by software (writing a logical
one to the I/O bit location). For measuring frequency only, the clearing of the ICF1 Flag is not required (if
an interrupt handler is used).
The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined
by the Waveform Generation mode (WGM1)
For detailed timing information refer to
The simplest mode of operation is the Normal mode (WGM13:0 = 0). In this mode the counting direction
is always up (incrementing), and no counter clear is performed. The counter simply overruns when it
passes its maximum 16-bit value (MAX = 0xFFFF) and then restarts from the BOTTOM (0x0000). In
normal operation the Timer/Counter Overflow Flag (TOV1) will be set in the same timer clock cycle as
the TCNT1 becomes zero. The TOV1 Flag in this case behaves like a 17th bit, except that it is only set,
(SeeFigure 11-2 on page
“Timer/Counter Timing Diagrams” on page
90). The edge detector is also identical.
AT90PWM81
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