R8A77850ADBGV#RD0Z Renesas Electronics America, R8A77850ADBGV#RD0Z Datasheet - Page 1086

• Manufacturer Part Number: R8A77850ADBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ADBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

21. Serial Communication Interface with FIFO (SCIF)
Legend:
x: Don't care
Notes: 1. An RXI interrupt request can be canceled by reading 1 from the RDF or DR flag in
Rev.1.00 Jan. 10, 2008 Page 1054 of 1658
REJ09B0261-0100
Bit
1
0
2. SCSMR and SCFCR settings must be made, the transmission format determined, and
3. SCSMR and SCFCR settings must be made, the reception format determined, and the
4. The output clock frequency is 16 times the bit rate.
5. The input clock frequency is 16 times the bit rate.
Bit Name
CKE1
CKE0
(For the relation between the value set in SCBRR and the baud rate generator, see
SCFSR, then clearing the flag to 0, or by clearing the RIE bit to 0. ERI and BRI interrupt
requests can be canceled by reading 1 from ER and BRK in SCFSR, or ORER flag in
SCFSR, then clearing the flag to 0, or by clearing the RIE and REIE bits to 0.
the transmit FIFO reset (the TFCL bit in SCFCR set to 1), before the TE bit is set to 1.
receive FIFO reset (the RFCL bit in SCFCR set to 1), before the RE bit is set to 1.
section 21.3.8, Bit Rate Register n (SCBRR).)
Initial
Value
0
0
R/W
R/W
R/W
Description
Clock Enable 1, 0
These bits select the SCIF clock source and whether to
enable or disable the clock output from the SCIF_SCK
pin. The CKE1 and CKE0 bits are used together to
specify whether the SCIF_SCK pin functions as a serial
clock output pin or a serial clock input pin. Note
however that the CKE0 bit setting is valid only when an
internal clock is selected as the SCIF clock source
(CKE1 = 0). When an external clock is selected (CKE1
= 1), the CKE0 bit setting is invalid. The CKE1 and
CKE0 bit must be set before determining the SCIF's
operating mode with SCSMR.
•
00: Internal clock/SCIF_SCK pin functions as port
01: Internal clock/SCIF_SCK pin functions as clock
1x: External clock/SCIF_SCK pin functions as clock
•
0x: Internal clock/SCIF_SCK pin functions as
1x: External clock/SCIF_SCK pin functions as
Asynchronous mode
according to the SCSPTR settings
output*
input*
Clocked synchronous mode
synchronization clock output
synchronization clock input
5
4