R8A77850ADBGV#RD0Z Renesas Electronics America, R8A77850ADBGV#RD0Z Datasheet - Page 1201

• Manufacturer Part Number: R8A77850ADBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ADBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

23.4.4
If any of the control bits, except for SPCR and the interrupt and chip select value bits of SPSCR,
are changed, then the HSPI software reset is generated. The receive and transmit FIFO pointers
can be initialized by the HSPI software reset. The data transmission after the HSPI software reset
should conform to transmitting and receiving protocol of HSPI and be performed from the
beginning; otherwise, correct operation is not guaranteed.
When asserting the HSPI_CS except when the master device is transferring data with the HSPI in
slave mode, set CSA again after a software reset. This prevents the HSPI from receiving erroneous
data.
23.4.5
SPCR also allows the user to define the shift timing for transmit data and polarity. The FBS bit in
SPCR allows selection between two different transfer formats. When CSA of SPSR is 0, the MSB
or LSB is valid at the falling edge of HSPI_CS. The CLKP bit in SPCR allows for control of the
polarity select block, shown in figure 23.1, which selects the edge of HSPI_CLK on which data is
shifted and sampled in the master and slave.
23.4.6
The master and slave can be considered linked together as a circular shift register synchronized
with HSPI_CLK. The transmit byte from the master is replaced with the receive byte from the
slave in eight HSPI_CLK cycles. Both the transmit and receive functions are double buffered to
allow for continuous reads and writes. When FIFO mode is enabled, 8-entry FIFOs are available
for both transmit and receive data.
HSPI Software Reset
Clock Polarity and Transmit Control
Transmit and Receive Routines
Rev.1.00 Jan. 10, 2008 Page 1169 of 1658
23. Serial Peripheral Interface (HSPI)
REJ09B0261-0100