R8A77850ADBGV#RD0Z Renesas Electronics America, R8A77850ADBGV#RD0Z Datasheet - Page 99

IC SUPERH MPU ROMLESS 436-BGA

R8A77850ADBGV#RD0Z

Manufacturer Part Number
R8A77850ADBGV#RD0Z
Description
IC SUPERH MPU ROMLESS 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R8A77850ADBGV#RD0Z

Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

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Manufacturer
Quantity
Price
Company:
Part Number:
R8A77850ADBGV#RD0ZR8A77850ADBGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Company:
Part Number:
R8A77850ADBGV#RD0Z
Manufacturer:
Renesas Electronics America
Quantity:
10 000
I1
(1-1) BF, BF/S, BT, BT/S, BRA, BSR:1 issue cycle + 0 to 3 branch cycles
(1-2) JSR, JMP, BRAF, BSRF: 1 issue cycle + 4 branch cycles
(1-3) RTS: 1 issue cycle + 0 to 4 branch cycles
(1-4) RTE: 4 issue cycles + 2 branch cycles
(1-5) TRAPA: 8 issue cycles + 5 cycles + 2 branch cycle
(1-6) SLEEP: 2 issue cycles
I2
I1
I1
I1
I1
I1
I3
I2
I2
I2
I2
ID
I2
Figure 4.2 Instruction Execution Patterns (1)
S1
ID
I3
I3
I3
I3
I3
E1s1
S2
ID
ID
ID
ID
ID
E2s2
S3
E1/S1 E2/s2 E3/s3
E1/S1 E2/S2 E3/S3
E1/S1 E2/S2 E3/S3
(I1)
s1
S1
ID
ID
E3s3
WB
E1s1
E1s1
(I1)
(I2)
(I1)
s2
S2
ID
WB
E2s2
E2s2
(I3)
(I2)
(I2)
(I1)
s3
ID
S3
(ID)
E3s3
ID
E3s3
(I3)
(I3)
WB
WB
WB
WB
WB
(I2)
Note:
E1s1
ID
(ID)
(ID)
WB
WB
(I3)
Note:
(Branch destination instruction)
It is 15 cycles to the ID stage
in the first instruction of exception handler
E2s2
E1s1
Note: The number of branch cycles may be
ID
In branch instructions that are categorized
as (1-1), the number of branch cycles
may be reduced by prefetching.
(ID)
Rev.1.00 Jan. 10, 2008 Page 67 of 1658
E3s3
E2s2
E1s1
(Branch destination instruction)
0 by prefetching instruction.
(Branch destination instruction)
ID
Note:
E3s3
E2s2
E1s1
(Branch destination instruction)
WB
ID
It is not constant cycles to
the clock halted period.
E2s2
E3s3
E1s1
WB
(I1)
ID
E2s2 E3s3 WB
E3s3
E1s1
WB
(I2)
E2s2 E3s3 WB
WB
(I3)
REJ09B0261-0100
(ID)
4. Pipelining

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