R8A77850ADBGV#RD0Z Renesas Electronics America, R8A77850ADBGV#RD0Z Datasheet - Page 293

• Manufacturer Part Number: R8A77850ADBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ADBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

9.5
9.5.1
In the event of simultaneous access to the same page from different buses, page conflict occurs.
Although each access is completed correctly, this kind of conflict tends to lower OL memory
accessibility. Therefore it is advisable to provide all possible preventative software measures. For
example, conflicts will not occur if each bus accesses different pages.
9.5.2
(1)
Read access from the operand bus is performed in one cycle when the access is made successively
to the same page but takes multiple cycles (a maximum of two wait cycles may be required) when
the access is made across pages or the previous access was made to memory other than OL
memory. For this reason, from the viewpoint of performance optimization, it is recommended to
design the software such that the page corresponding to the address for read access from the
operand bus does not change so often.
(2)
Access from the instruction bus is performed in one cycle when the access is made successively to
the same page but takes multiple cycles (a maximum of two wait cycles may be required) when
the access is made across pages or the previous access was made to memory other than IL
memory. For this reason, from the viewpoint of performance optimization, it is recommended to
design the software such that the target page does not change so often in access from the
instruction bus. For example, allocating a separate program for each page will deliver better
efficiency.
9.5.3
(1)
In order to allocate instructions in the OL memory, write an instruction to the OL memory,
execute the following sequence, then branch to the rewritten instruction.
• SYNCO
• ICBI @Rn
In this case, the target for the ICBI instruction can be any address (OL memory address may be
possible) within the range where no address error exception occurs, and cache hit/miss is possible.
OL Memory
IL Memory
OL Memory
Usage Notes
Page Conflict
Access Across Different Pages
On-Chip Memory Coherency
Rev.1.00 Jan. 10, 2008 Page 261 of 1658
9. On-Chip Memory
REJ09B0261-0100