R8A77850ADBGV#RD0Z Renesas Electronics America, R8A77850ADBGV#RD0Z Datasheet - Page 624

• Manufacturer Part Number: R8A77850ADBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ADBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

13. PCI Controller (PCIC)
Rev.1.00 Jan. 10, 2008 Page 592 of 1658
REJ09B0261-0100
Bit
2
1
0
Bit Name
IOCS
RSTCTL
CFINIT
Initial
Value
0
0
0
R/W
SH: R/W
PCI: R
SH: R/W
PCI: R
SH: R/W
PCI: R
Description
INTA Output
Controls the INTA output by software. This bit is valid
only when the PCIC operates in normal mode.
0: The INTA pin is in the high-impedance state (driven
1: Asserts INTA (output at low level)
PCIRST Output
Controls the PCIRST pin state by setting this bit to 1.
The PCIRST pin is output at low level at a power-on
reset.
0: Negates PCIRST (output at high level)
1: Asserts PCIRST (output at low level)
PCIC Internal Register Initialization Control
This bit should be set to 1 after the PCIC internal
registers are initialized. Setting this bit enables
accesses from the PCI bus. During initialization in
host mode, the bus mastership is not given to the
other devices on the PCI bus. In normal mode, the
PCIC returns RETRY without accepting the access
from the PCI bus when it is accessed from the PCI
bus.
0: Initialization being performed
1: Initialization completed
high by an on-chip pull-up resistor)