R8A77850ADBGV#RD0Z Renesas Electronics America, R8A77850ADBGV#RD0Z Datasheet - Page 1379
![IC SUPERH MPU ROMLESS 436-BGA](/photos/28/62/286211/436-bfbga_sml.jpg)
R8A77850ADBGV#RD0Z
Manufacturer Part Number
R8A77850ADBGV#RD0Z
Description
IC SUPERH MPU ROMLESS 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77850AADBGV.pdf
(1694 pages)
Specifications of R8A77850ADBGV#RD0Z
Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R8A77850ADBGV#RD0ZR8A77850ADBGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Bit
25
24
23, 22
21
20
19, 18
17
Bit Name
CDSRC
DOSR
—
SELRW
DOADR
ADRCNT
[1:0]
DOCMD2
Initial
Value
0
0
All 0
0
0
00
0
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
Description
Data Buffer Specification
Specifies the data buffer to be read from or written to in
the data stage* in command access mode.
0: Specifies FLDATAR as the data buffer.
1: Specifies FLDTFIFO as the data buffer.
Status Read Check
Specifies whether the status read is performed after the
second command has been issued in command access
mode.
0: Performs no status read
1: Performs status read
Reserved
These bits are always read as 0. The write value should
always be 0.
Data Read/Write Specification
Specifies whether the direction is read or write in data
stage.
0: Read
1: Write
Address Stage Execution Specification
Specifies whether the address stage* is executed in
command access mode.
0: Performs no address stage
1: Performs address stage
Address Issue Byte Count Specification
Specify the number of bytes for the address data to be
issued in address stage*.
00: Issue 1-byte address
01: Issue 2-byte address
10: Issue 3-byte address
11: Issue 4-byte address
Second Command Stage* Execution Specification
Specifies whether the second command stage* is
executed in command access mode.
0: Does not execute the second command stage
1: Executes the second command stage
27. NAND Flash Memory Controller (FLCTL)
Rev.1.00 Jan. 10, 2008 Page 1347 of 1658
REJ09B0261-0100
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