R8A77850ADBGV#RD0Z Renesas Electronics America, R8A77850ADBGV#RD0Z Datasheet - Page 1202
![IC SUPERH MPU ROMLESS 436-BGA](/photos/28/62/286211/436-bfbga_sml.jpg)
R8A77850ADBGV#RD0Z
Manufacturer Part Number
R8A77850ADBGV#RD0Z
Description
IC SUPERH MPU ROMLESS 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77850AADBGV.pdf
(1694 pages)
Specifications of R8A77850ADBGV#RD0Z
Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R8A77850ADBGV#RD0ZR8A77850ADBGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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23. Serial Peripheral Interface (HSPI)
23.4.7
The interrupt timing when the flags of the status register (SPSR) and the system control register
(SPSCR) are set is shown in figure 23.7.
If an interrupt cause (receive FIFO halfway, etc.) occurs, it is reflected to the status register
(SPSR) in synchronization with Pck, and an interrupt occurs.
23.4.8
The HSPI operates in synchronization with the bus clock. Module standby mode is
enabled/disabled by the MSTP2 bit of the CPG module standby control register 0 (MSTPCR0).
Take the following steps to enter module standby mode.
1. Check that all data transfers have been completed. The transmit buffer (or FIFO) must be
2. Disable all DMA requests, interrupt requests, and FIFO mode.
3. Set the MSTP2 bit of the standby control register 0 (MSTPCR0).
To activate the HSPI, write 0 to the MSTP2 bit of the standby control register 0 (MSTPCR0).
Rev.1.00 Jan. 10, 2008 Page 1170 of 1658
REJ09B0261-0100
empty and the receive buffer (or FIFO) must be read until the receive buffer becomes empty.
Flags and Interrupt Timing
Low-Power Consumption and Clock Synchronization
Internal interrupt
Flags (SPSR)
HSPI_CLK
HSPI_CS
Interrupt
Pck
Figure 23.7 Flags and Interrupt Timing
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