R8A77850ADBGV#RD0Z Renesas Electronics America, R8A77850ADBGV#RD0Z Datasheet - Page 236

• Manufacturer Part Number: R8A77850ADBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ADBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

7. Memory Management Unit (MMU)
7.8.6
When using 32-bit address extended mode, note that the items described in this section are
extended or changed as follows.
(1)
The SE bit is added in bit 31 in the control register (PASCR). The bits 6 to 0 of the UB in the
PASCR are invalid (Note that the bit 7 of the UB is still valid). When writing to the P1 or P2 area,
the UB bit in the PMB controls whether a buffered write is performed or not. When the MMU is
enabled, the UB bit in the TLB controls writing to the P0, P3, or U0 area. When the MMU is
disabled, writing to the P0, P3, or U0 area is always performed as a buffered write.
Rev.1.00 Jan. 10, 2008 Page 204 of 1658
REJ09B0261-0100
Bit
31
PASCR
Notes on Using 32-Bit Address Extended Mode
Bit Name
SE
Address field
Address field
Data field
Data field
PPN:
SZ:
Figure 7.28 Memory-Mapped PMB Address Array
V:
E:
31
31
31
31
VPN:
1 1 1 1 0 1 1 1 0 0 0 1
Figure 7.29 Memory-Mapped PMB Data Array
1 1 1 1 0
Physical page number
Validity bit
Entry
Page size bits
Initial
Value
0
V:
E:
Physical page number
Validity bit
Entry
VPN
PPN
1 1 0
R/W
R/W
24
24
23
23
0 0 0
Description
0: 29-bit address mode
1: 32-bit address extended mode
20
20
1
WT:
UB:
19
19
0 0 0 0 0
0 0 0 0 0 0 0 0
C:
:
Buffered write bit
Cacheability bit
Write-through bit
Reserved bits (write value should be 0
and read value is undefined )
: Reserved bits (write value should be 0
and read value is undefined )
0 0 0
12 11
12 11
10 9 8 7
E
E
UB
8 7
V
8 7
8
V
0 0 0 0 0 0 0 0
0
6 5
0 0 0 0 0
SZ
4 3
C
2 1 0
0 0
WT
0
0
0