R8A77850ADBGV#RD0Z Renesas Electronics America, R8A77850ADBGV#RD0Z Datasheet - Page 1378
![IC SUPERH MPU ROMLESS 436-BGA](/photos/28/62/286211/436-bfbga_sml.jpg)
R8A77850ADBGV#RD0Z
Manufacturer Part Number
R8A77850ADBGV#RD0Z
Description
IC SUPERH MPU ROMLESS 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77850AADBGV.pdf
(1694 pages)
Specifications of R8A77850ADBGV#RD0Z
Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R8A77850ADBGV#RD0ZR8A77850ADBGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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27. NAND Flash Memory Controller (FLCTL)
27.3.2
FLCMDCR is a 32-bit readable/writable register that issues a command in command access mode,
specifies address issue, and specifies destination of data to be input or output. In sector access
mode, FLCMDCR specifies the number of sector transfers.
Rev.1.00 Jan. 10, 2008 Page 1346 of 1658
REJ09B0261-0100
Initial value:
Initial value:
Bit
31
30 to 27
26
R/W:
R/W:
Bit:
Bit:
Command Control Register (FLCMDCR)
Bit Name
ADRCNT2 0
SCTCNT
[19:16]
ADRMD
CNT2
R/W
R/W
ADR
31
15
0
0
R/W
R/W
30
14
0
0
SCTCNT[19:16]
R/W
R/W
29
13
Initial
Value
All 0
0
0
0
R/W
R/W
28
12
0
0
R/W
R/W
R/W
R/W
R/W
R/W
27
11
0
0
ADRMD
R/W
R/W
26
10
0
0
Description
Address Issue Byte Number Specification
Specifies the number of bytes issued in the address
stage.
0: Issues address as many as the bytes specified in
1: Issues 5-byte address
Note: Set ADRCNT1 and ADRCNT0 to 0.
Selector Transfer Count Specification [19:16]
These bits are extended bits of bits SCTCNT[15:0].
When bits SCTCNT[19:16] and bits SCTCNT[15:0] are
put together, these bits operate as a 20-bit counter of
bits SCTCNT[19:0].
Sector Access Address Specification
This bit is invalid in command access mode. This bit is
valid only in sector access mode.
0: The value of the address register is handled as a
1: The value of the address register is output as the
Note: Clear this bit to 0 in continuous sector access.
CDSRC
R/W
R/W
25
0
9
0
physical sector number. Always use this value in
sector access.
address of flash memory.
ADRCNT1 and ADRCNT0
SCTCNT[15:0]
DOSR
R/W
R/W
24
0
8
0
R/W
23
R
0
7
0
R/W
22
R
0
6
0
SELRW DOADR
R/W
R/W
21
0
5
0
R/W
R/W
20
0
4
0
ADRCNT[1:0]
R/W
R/W
19
0
3
0
R/W
R/W
18
0
2
0
DOCMD2 DOCMD1
R/W
R/W
17
0
1
0
R/W
R/W
16
0
0
0
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