R8A77850ADBGV#RD0Z Renesas Electronics America, R8A77850ADBGV#RD0Z Datasheet - Page 714

• Manufacturer Part Number: R8A77850ADBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ADBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

14. Direct Memory Access Controller (DMAC)
Rev.1.00 Jan. 10, 2008 Page 682 of 1658
REJ09B0261-0100
Bit
27 to 25
24
23
22
Bit Name
RPT[2:0]
⎯
DO
RL
Initial
Value
000
0
0
0
R/W
R/W
R
R/W
R/W
Descriptions
DMA Setting Update Specification
These bits are valid in only CHCR0 to CHCR3, and
CHCR6 to CHCR9.
000: Normal mode
001: Repeat mode
010: Repeat mode
011: Repeat mode
100: Reserved (setting prohibited)
101: Reload mode
110: Reload mode
111: Reload mode
Reserved
This bit is always read as 0. The write value should
always be 0.
DMA Overrun
Selects whether DREQ is detected by overrun 0 or by
overrun 1. This bit is valid in only CHCR0 to CHCR3.
0: Detects DREQ by overrun 0
1: Detects DREQ by overrun 1
Request Check Level
Selects whether the DRAK signal output is an active-
high or active-low. This bit valid in only CHCR0 to
CHCR3. If the DRAK active direction is changed,
reflecting the change on the external pins requires one
cycle of the external bus clock after writing to the
register is completed.
0: DRAK is an active-low output
1: DRAK is an active-high output
SAR/DAR/TCR are repeated
DAR/TCR is repeated
SAR/TCR is repeated
SAR/DAR is reloaded
DAR is reloaded
SAR is reloaded