R8A77850ADBGV#RD0Z Renesas Electronics America, R8A77850ADBGV#RD0Z Datasheet - Page 955
![IC SUPERH MPU ROMLESS 436-BGA](/photos/28/62/286211/436-bfbga_sml.jpg)
R8A77850ADBGV#RD0Z
Manufacturer Part Number
R8A77850ADBGV#RD0Z
Description
IC SUPERH MPU ROMLESS 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77850AADBGV.pdf
(1694 pages)
Specifications of R8A77850ADBGV#RD0Z
Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R8A77850ADBGV#RD0ZR8A77850ADBGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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19.3.53 Output Signal Timing Adjustment Register (OTAR)
The output signal timing adjustment register (OTAR) selects the timing for the output signal.
For information on adjustment timing, refer to section 19.5.5, Output Signal Timing Adjustment.
Internal update:
Internal update:
Bit
31
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
Bit Name
⎯
31
15
—
—
R
R
0
0
R/W
30
14
—
R
0
0
Initial
Value
0
R/W
DEA
29
13
—
R
0
0
R/W
28
12
—
R
0
0
R/W
R
27
11
—
—
R
R
0
0
Internal
Update
⎯
R/W
R/W
26
10
0
0
CLAMPA
CDEA
R/W
R/W
25
0
9
0
Description
Reserved
This bit is always read as 0. The write value
should always be 0.
R/W
R/W
24
0
8
0
23
—
—
R
R
0
7
0
Rev.1.00 Jan. 10, 2008 Page 923 of 1658
R/W
R/W
22
0
6
0
DRGBA
DISPA
R/W
R/W
21
0
5
0
R/W
R/W
20
0
4
0
19. Display Unit (DU)
19
—
—
R
R
0
3
0
REJ09B0261-0100
R/W
18
—
R
0
2
0
SYNCA
R/W
17
—
R
0
1
0
R/W
16
—
R
0
0
0
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