R8A77850ADBGV#RD0Z Renesas Electronics America, R8A77850ADBGV#RD0Z Datasheet - Page 862
![IC SUPERH MPU ROMLESS 436-BGA](/photos/28/62/286211/436-bfbga_sml.jpg)
R8A77850ADBGV#RD0Z
Manufacturer Part Number
R8A77850ADBGV#RD0Z
Description
IC SUPERH MPU ROMLESS 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77850AADBGV.pdf
(1694 pages)
Specifications of R8A77850ADBGV#RD0Z
Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R8A77850ADBGV#RD0ZR8A77850ADBGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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19. Display Unit (DU)
Table 19.3 Status of Registers in Each Processing Mode
Rev.1.00 Jan. 10, 2008 Page 830 of 1658
REJ09B0261-0100
Register Name
Display system
control register
Display mode
register
Display status
register
Display status
register clear
register
Display interrupt
enable register
Color palette
control register
Display plane
priority order
register
Display extension
function enable
register
Abbr.
DSYSR
DSMR
DSSR
DSRCR
DIER
CPCR
DPPR
DEFR
Power-On
Reset by
PRESET
Pin/ WDT/
H-UDI
H'00000280 Retained
H'00000000 Retained
H'30000000 Retained
Undefined
H'00000000 Retained
H'00000000 Retained
H'00543210 Retained
H'00000000 Retained
Display control registers
Manual
Reset by
WDT
Retained
Sleep by
Sleep
Instruction
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Module
Standby
Retained Retained DSEC
Retained Retained All bits
Retained Retained None
Retained Retained None
Retained Retained None
Retained Retained All bits
Retained Retained All bits
Retained Retained None
Deep
Sleep
Bits with
Internal Update
Function
DEN
except the
following bits
which are
updated by the
DRES bit in the
display system
control register
(DSYSR):
VSPM
ODPM
DIPM
CSPM
DIL
VSL
HSL
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