R8A77850ADBGV#RD0Z Renesas Electronics America, R8A77850ADBGV#RD0Z Datasheet - Page 1489
R8A77850ADBGV#RD0Z
Manufacturer Part Number
R8A77850ADBGV#RD0Z
Description
IC SUPERH MPU ROMLESS 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77850AADBGV.pdf
(1694 pages)
Specifications of R8A77850ADBGV#RD0Z
Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R8A77850ADBGV#RD0ZR8A77850ADBGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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29.2.1
CBR0 and CBR1 are readable/writable 32-bit registers which specify the break conditions for
channels 0 and 1, respectively. The following break conditions can be set in the CBR0 and CBR1:
(1) whether or not to include the match flag in the conditions, (2) whether or not to include the
ASID, and the ASID value when included, (3) whether or not to include the data value, (4)
operand size, (5) whether or not to include the execution count, (6) bus type, (7) instruction fetch
cycle or operand access cycle, and (8) read or write access cycle.
• CBR0
Bit
31
30
Initial value :
Initial value :
R/W:
R/W:
Bit :
Bit :
Match Condition Setting Registers 0 and 1 (CBR0 and CBR1)
Bit Name
MFE
AIE
MFE
R/W
31
15
R
0
0
R/W
R/W
AIE
30
14
0
0
R/W
R/W
SZ
29
13
Initial
Value
0
0
1
0
R/W
R/W
28
12
0
0
R/W
27
11
R/W
R/W
R/W
R
0
0
MFI
R/W
26
10
R
0
0
Description
Match Flag Enable
Specifies whether or not to include the match flag value
specified by the MFI bit of this register in the match
conditions. When the specified match flag value is 1, the
condition is determined to be satisfied.
0: The match flag is not included in the match conditions;
1: The match flag is included in the match conditions.
ASID Enable
Specifies whether or not to include the ASID specified by
the AIV bit of this register in the match conditions.
0: The ASID is not included in the match conditions;
1: The ASID is included in the match conditions.
thus, not checked.
thus, not checked.
R/W
25
R
0
9
0
R/W
24
R
0
8
0
R/W
R/W
23
0
7
0
CD
Rev.1.00 Jan. 10, 2008 Page 1457 of 1658
R/W
R/W
22
0
6
0
R/W
R/W
21
0
5
0
29. User Break Controller (UBC)
ID
R/W
R/W
20
0
4
0
AIV
R/W
19
R
3
0
0
REJ09B0261-0100
R/W
R/W
18
0
2
0
RW
R/W
R/W
17
0
1
0
R/W
R/W
CE
16
0
0
0
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