R8A77850ADBGV#RD0Z Renesas Electronics America, R8A77850ADBGV#RD0Z Datasheet - Page 23

• Manufacturer Part Number: R8A77850ADBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ADBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

19.5 Display Control.................................................................................................................. 956
19.6 Power-Down Sequence ...................................................................................................... 968
Section 20 Graphics Data Translation Accelerator (GDTA)
20.1 Features.............................................................................................................................. 969
20.2 GDTA Address Space........................................................................................................ 973
20.3 Register Descriptions ......................................................................................................... 974
19.4.12 Scroll Display ..................................................................................................... 950
19.4.13 Wraparound Display ........................................................................................... 951
19.4.14 Upper-Left Overflow Display............................................................................. 952
19.4.15 Double Buffer Control ........................................................................................ 953
19.4.16 Sync Mode .......................................................................................................... 954
19.5.1
19.5.2
19.5.3
19.5.4
19.5.5
19.5.6
19.6.1
19.6.2
20.3.1
20.3.2
20.3.3
20.3.4
20.3.5
20.3.6
20.3.7
20.3.8
20.3.9
20.3.10 GA Buffer RAM 0 Data Alignment Register (DCP_CTL)................................. 988
20.3.11 GA Buffer RAM 1 Data Alignment Register (DID_CTL) ................................. 989
20.3.12 CL Command FIFO (CLCF) .............................................................................. 990
20.3.13 CL Control Register (CLCR).............................................................................. 991
20.3.14 CL Status Register (CLSR)................................................................................. 993
20.3.15 CL Frame Width Setting Register (CLWR) ....................................................... 994
20.3.16 CL Frame Height Setting Register (CLHR) ....................................................... 995
20.3.17 CL Input Y Padding Size Setting Register (CLIYPR)........................................ 996
20.3.18 CL Input UV Padding Size Setting Register (CLIUVPR) .................................. 997
20.3.19 CL Output Padding Size Setting Register (CLOPR) .......................................... 998
20.3.20 CL Palette Pointer Register (CLPLPR) .............................................................. 999
Display Timing Generation ................................................................................ 956
CSYNC............................................................................................................... 959
Scan Method ....................................................................................................... 961
Color Detection................................................................................................... 965
Output Signal Timing Adjustment...................................................................... 966
CLAMP Signal and DE Signal ........................................................................... 967
Procedures before Executing the Power-Down Sequence .................................. 968
Resetting the Power-Down Sequence ................................................................. 968
GA Mask Register (GACMR) ............................................................................ 979
GA Enable Register (GACER) ........................................................................... 980
GA Interrupt Source Indicating Register (GACISR) .......................................... 981
GA Interrupt Source Indication Clear Register (GACICR) ................................ 982
GA Interrupt Enable Register (GACIER)........................................................... 983
GA CL Input Data Alignment Register (DRCL_CTL)....................................... 984
GA CL Output Data Alignment Register (DWCL_CTL)................................... 985
GA MC Input Data Alignment Register (DRMC_CTL) .................................... 986
GA MC Output Data Alignment Register (DWMC_CTL)................................. 987
Rev.1.00 Jan. 10, 2008 Page xxi of xxx
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REJ09B0261-0100